DE69322348D1 - Verfahren für vertiefte, selbstausgerichtete Basisstruktur mit niedrigem Widerstand - Google Patents

Verfahren für vertiefte, selbstausgerichtete Basisstruktur mit niedrigem Widerstand

Info

Publication number
DE69322348D1
DE69322348D1 DE69322348T DE69322348T DE69322348D1 DE 69322348 D1 DE69322348 D1 DE 69322348D1 DE 69322348 T DE69322348 T DE 69322348T DE 69322348 T DE69322348 T DE 69322348T DE 69322348 D1 DE69322348 D1 DE 69322348D1
Authority
DE
Germany
Prior art keywords
recessed
self
low resistance
base structure
aligned base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69322348T
Other languages
English (en)
Other versions
DE69322348T2 (de
Inventor
William P Imhauser
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69322348D1 publication Critical patent/DE69322348D1/de
Application granted granted Critical
Publication of DE69322348T2 publication Critical patent/DE69322348T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors
    • H01L29/66295—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor
    • H01L29/66303—Silicon vertical transistors with main current going through the whole silicon substrate, e.g. power bipolar transistor with multi-emitter, e.g. interdigitated, multi-cellular or distributed emitter
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0804—Emitter regions of bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/01—Bipolar transistors-ion implantation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/102—Mask alignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Bipolar Transistors (AREA)
DE69322348T 1992-09-25 1993-09-17 Verfahren für vertiefte, selbstausgerichtete Basisstruktur mit niedrigem Widerstand Expired - Fee Related DE69322348T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/951,162 US5328857A (en) 1992-09-25 1992-09-25 Method of forming a bilevel, self aligned, low base resistance semiconductor structure

Publications (2)

Publication Number Publication Date
DE69322348D1 true DE69322348D1 (de) 1999-01-14
DE69322348T2 DE69322348T2 (de) 1999-04-29

Family

ID=25491349

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69322348T Expired - Fee Related DE69322348T2 (de) 1992-09-25 1993-09-17 Verfahren für vertiefte, selbstausgerichtete Basisstruktur mit niedrigem Widerstand

Country Status (3)

Country Link
US (1) US5328857A (de)
EP (1) EP0589631B1 (de)
DE (1) DE69322348T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5416032A (en) * 1994-06-24 1995-05-16 Sgs-Thomson Microelectronics, Inc. Method of making a high conductivity p-plus region for self-aligned, shallow diffused, bipolar transistors
US5455449A (en) * 1994-06-30 1995-10-03 National Semiconductor Corporation Offset lattice bipolar transistor architecture
US5631495A (en) * 1994-11-29 1997-05-20 International Business Machines Corporation High performance bipolar devices with plurality of base contact regions formed around the emitter layer
DE19832329A1 (de) * 1997-07-31 1999-02-04 Siemens Ag Verfahren zur Strukturierung von Halbleitern mit hoher Präzision, guter Homogenität und Reproduzierbarkeit
KR100340648B1 (ko) * 2001-10-22 2002-06-20 염병렬 바이폴라 트랜지스터

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4433470A (en) * 1981-05-19 1984-02-28 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing semiconductor device utilizing selective etching and diffusion
US4539742A (en) * 1981-06-22 1985-09-10 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor device and method for manufacturing the same
US4433471A (en) * 1982-01-18 1984-02-28 Fairchild Camera & Instrument Corporation Method for the formation of high density memory cells using ion implantation techniques
US4625388A (en) * 1982-04-26 1986-12-02 Acrian, Inc. Method of fabricating mesa MOSFET using overhang mask and resulting structure
US4510016A (en) * 1982-12-09 1985-04-09 Gte Laboratories Method of fabricating submicron silicon structures such as permeable base transistors
JPS63249370A (ja) * 1987-04-06 1988-10-17 Toshiba Corp 半導体装置およびその製造方法
JPH06101473B2 (ja) * 1988-12-05 1994-12-12 日本電気株式会社 半導体装置
JPH07114210B2 (ja) * 1990-01-26 1995-12-06 株式会社東芝 半導体装置の製造方法

Also Published As

Publication number Publication date
DE69322348T2 (de) 1999-04-29
EP0589631B1 (de) 1998-12-02
EP0589631A1 (de) 1994-03-30
US5328857A (en) 1994-07-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee