DE69306342T2 - Signal integration circuit - Google Patents

Description

FIELD OF THE INVENTION

The present invention relates to a signal integration circuit effective for weighted integration of signals.

BACKGROUND OF THE INVENTION

Conventionally, a device having a plurality of inputs has become necessary for integrating signals, and a device having a plurality of inputs and a different type of devices or program libraries corresponding to a number of inputs has also become necessary. Generally, a multiplication circuit for giving a given weight and integrating each signal has become necessary. To realize this, the structure of the circuit has become complex.

SUMMARY OF THE INVENTION

The present invention solves the above conventional problems and has an object to provide a signal integration circuit for integrating a weighted signal by a simple circuit.

A signal integration circuit according to the present invention controls the threshold value of a MOSFET by a voltage integrated by giving an electric charge to a parallel capacitance, and generates an output pulse signal by eliminating a reference sawtooth signal with the threshold value. Each capacitance is controlled by connecting the power source that supplies the predetermined voltage, with the capacitance charged synchronously with the input pulse signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a circuit embodying the signal integration circuit according to the present invention.

Figure 2 shows a circuit of an input module of the embodiment of Figure 1.

Figure 3 (a) is a graphical representation of the relationship between the input pulse signal and the input module output.

Figure 3 (b) is a graphical representation of the relationship between the reference sawtooth waveform and the threshold voltage.

Figure 3 (c) is a graphical representation of the relationship between the reference sawtooth waveform and the output pulse signal.

PREFERRED EMBODIMENT OF THE PRESENT INVENTION

Hereinafter, an embodiment of the signal integration circuit according to the present invention will be described with reference to the accompanying drawings.

In Figure 1, the signal integration circuit connects a plurality of input modules WS₁, WS₂, ..., Wsn to a MOSFET ("T₁" hereinafter) via parallel capacitances C₁, C₂, ..., Cn. The drain of T₁ is connected to an input power supply Vcc. The source of T₁ is grounded via a capacitance Cg1. A voltage D₀ is generated in the source of T₁ according to the voltage of the gate.

The reference sawtooth signal "RP" is input to the gate of T₁ through a capacitance "Cr". The voltage of the gate of T₁ is the same as the summation of the electric charges from C₁ to Cn and Cr. Here, the threshold voltage is assumed to be 0V, and RP is the sawtooth waveform in minus 0V of the maximum value as shown in Figure 3 (b). When the voltage of the gate increases through the capacitances from C₁ to Cn, the effect is produced which is the same as that when the threshold value for RP becomes lower. It is shown in Figure 3 (b) with a broken line Vt. T₁ becomes conductive in the part above Vi. The output of T₁ is the output pulse signal D₀ in Figure 3 (c).

As shown in Figure 2, in the input module WSi, an input pulse signal Di is input to the drain of the MOSFET ("T2" hereinafter), and the source of T2 is an output terminal of the capacitance Ci. The source of T2 is grounded thereto via the capacitance Cg2 and the resistance R2. Under charging and discharging electricity at the predetermined time, a voltage V corresponding to Di is generated. Figure 3 (a) shows an example of the relationship between Di and Vi.

The capacitance Cg3 is connected to the gate of T₂ for setting a gate voltage to which the MOSFET ("T₃" hereinafter) is connected for charging electricity. A weight setting pulse signal Wi is input to the gate of T₃. Cg3 is charged by the power supply Vcc while the pulse is at a high level, thus setting the voltage of the gate of T₂. The voltage of the gate is equivalent to the weight. The speed of charging Cg2 becomes higher because the voltage between the source and drain of T₂ increases in accordance with the voltage of the gate, thus increasing the maximum value of Vi. When the drain voltage of T₂ is OV, the electricity is discharged from the source to the drain. If the constant is appropriate, R₂ is not necessary.

The above description shows that the signal integration circuit changes the voltage of the threshold value of T₁ according to the duty ratio of the weighted input pulse signal Di and controls the duty ratio of the output pulse signal by this. Therefore, it is possible to output the result of a weighted pulse input.

As mentioned, the signal integration circuit according to the present invention controls the threshold value of the MOSFET by a voltage integrated by a given electric charge to a parallel capacitance, generates an output pulse signal by eliminating a reference sawtooth waveform with the threshold. Each capacitance is charged by connecting the power source having the predetermined voltage to the capacitance in synchronization with the input pulse signal. Therefore, it is possible to realize the integration of a weighted signal by a fairly simple circuit.

Claims (1)

1. Signal integration circuit with: a first MOSFET (T₁), the drain terminal of which is connected to a source (Vcc) and the gate terminal of which is connected to a multiplicity of first capacitors (C₁...CnCr) connected in parallel, and an input device (WS₁...WSn) connected to each capacitor; characterized in that each input device comprises: a second MOSFET (T₂) whose source terminal is connected to the first capacitor via a resistor (R₁), whose drain terminal receives a first input signal (Di) and whose gate terminal is grounded via a second capacitor, and a third MOSFET (T₃) whose source terminal is connected to the gate terminal of the second MOSFET, whose drain terminal is connected to a power source and whose gate terminal receives a second pulse signal to set a weight, wherein the gate terminal of the first MOSFET (T₁) receives a reference sawtooth signal, the source terminal of the first MOSFET is grounded via a third capacitance (Cg1), and the output pulse signal (D₀) is output from the source terminal of the first MOSFET (T₁).