DE69225345D1 - Eine Signalverarbeitungseinrichtung und ein Verfahren zum Übertragen von Signalen - Google Patents
Eine Signalverarbeitungseinrichtung und ein Verfahren zum Übertragen von SignalenInfo
- Publication number
- DE69225345D1 DE69225345D1 DE69225345T DE69225345T DE69225345D1 DE 69225345 D1 DE69225345 D1 DE 69225345D1 DE 69225345 T DE69225345 T DE 69225345T DE 69225345 T DE69225345 T DE 69225345T DE 69225345 D1 DE69225345 D1 DE 69225345D1
- Authority
- DE
- Germany
- Prior art keywords
- processing device
- signal processing
- transmitting signals
- transmitting
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017545—Coupling arrangements; Impedance matching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356104—Bistable circuits using complementary field-effect transistors
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/04—Shaping pulses by increasing duration; by decreasing duration
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/01—Shaping pulses
- H03K5/12—Shaping pulses by steepening leading or trailing edges
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Nonlinear Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1237791 | 1991-01-10 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69225345D1 true DE69225345D1 (de) | 1998-06-10 |
DE69225345T2 DE69225345T2 (de) | 1998-09-03 |
Family
ID=11803585
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69225345T Expired - Lifetime DE69225345T2 (de) | 1991-01-10 | 1992-01-10 | Eine Signalverarbeitungseinrichtung und ein Verfahren zum Übertragen von Signalen |
Country Status (3)
Country | Link |
---|---|
US (1) | US5619159A (de) |
EP (1) | EP0494832B1 (de) |
DE (1) | DE69225345T2 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6255852B1 (en) * | 1999-02-09 | 2001-07-03 | Micron Technology, Inc. | Current mode signal interconnects and CMOS amplifier |
US7554829B2 (en) * | 1999-07-30 | 2009-06-30 | Micron Technology, Inc. | Transmission lines for CMOS integrated circuits |
US7101770B2 (en) * | 2002-01-30 | 2006-09-05 | Micron Technology, Inc. | Capacitive techniques to reduce noise in high speed interconnections |
US7235457B2 (en) | 2002-03-13 | 2007-06-26 | Micron Technology, Inc. | High permeability layered films to reduce noise in high speed interconnects |
US6900116B2 (en) * | 2002-03-13 | 2005-05-31 | Micron Technology Inc. | High permeability thin films and patterned thin films to reduce noise in high speed interconnections |
US6846738B2 (en) * | 2002-03-13 | 2005-01-25 | Micron Technology, Inc. | High permeability composite films to reduce noise in high speed interconnects |
US7589029B2 (en) | 2002-05-02 | 2009-09-15 | Micron Technology, Inc. | Atomic layer deposition and conversion |
US7160577B2 (en) | 2002-05-02 | 2007-01-09 | Micron Technology, Inc. | Methods for atomic-layer deposition of aluminum oxides in integrated circuits |
US6970053B2 (en) * | 2003-05-22 | 2005-11-29 | Micron Technology, Inc. | Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection |
US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL294439A (de) * | 1959-12-21 | |||
US3191055A (en) * | 1960-03-21 | 1965-06-22 | Ibm | Superconductive transmission line |
JPS62214714A (ja) * | 1986-03-15 | 1987-09-21 | Fujitsu Ltd | ノイズ対策回路を備えたlsi装置 |
JPH0618197B2 (ja) * | 1987-07-30 | 1994-03-09 | 日本電気株式会社 | 超伝導モノリシックマイクロ波集積回路 |
JP2538609B2 (ja) * | 1987-09-01 | 1996-09-25 | 富士通株式会社 | ゲ―トアレ― |
US4837609A (en) * | 1987-09-09 | 1989-06-06 | American Telephone And Telegraph Company, At&T Bell Laboratories | Semiconductor devices having superconducting interconnects |
JPH0710005B2 (ja) * | 1989-08-31 | 1995-02-01 | アメリカン テレフォン アンド テレグラフ カムパニー | 超伝導体相互接続装置 |
JPH1062020A (ja) * | 1996-08-22 | 1998-03-06 | Matsushita Refrig Co Ltd | 蓄熱式空気調和機 |
-
1992
- 1992-01-10 DE DE69225345T patent/DE69225345T2/de not_active Expired - Lifetime
- 1992-01-10 EP EP92400072A patent/EP0494832B1/de not_active Expired - Lifetime
-
1995
- 1995-08-09 US US08/513,031 patent/US5619159A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0494832A3 (en) | 1992-12-16 |
EP0494832A2 (de) | 1992-07-15 |
DE69225345T2 (de) | 1998-09-03 |
US5619159A (en) | 1997-04-08 |
EP0494832B1 (de) | 1998-05-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: SHARP K.K., OSAKA, JP |
|
8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |