DE69211175T2 - Sputterverfahren zum Bilden einer Aluminiumschicht auf einem gestuften Wafer - Google Patents

Sputterverfahren zum Bilden einer Aluminiumschicht auf einem gestuften Wafer

Info

Publication number
DE69211175T2
DE69211175T2 DE69211175T DE69211175T DE69211175T2 DE 69211175 T2 DE69211175 T2 DE 69211175T2 DE 69211175 T DE69211175 T DE 69211175T DE 69211175 T DE69211175 T DE 69211175T DE 69211175 T2 DE69211175 T2 DE 69211175T2
Authority
DE
Germany
Prior art keywords
forming
aluminum layer
sputtering process
stepped wafer
stepped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69211175T
Other languages
English (en)
Other versions
DE69211175D1 (de
Inventor
Chien-Rhone Wang
Haim Gilboa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Application granted granted Critical
Publication of DE69211175D1 publication Critical patent/DE69211175D1/de
Publication of DE69211175T2 publication Critical patent/DE69211175T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Physical Vapour Deposition (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE69211175T 1991-02-12 1992-02-12 Sputterverfahren zum Bilden einer Aluminiumschicht auf einem gestuften Wafer Expired - Fee Related DE69211175T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US65814091A 1991-02-12 1991-02-12

Publications (2)

Publication Number Publication Date
DE69211175D1 DE69211175D1 (de) 1996-07-11
DE69211175T2 true DE69211175T2 (de) 1997-02-06

Family

ID=24640062

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69211175T Expired - Fee Related DE69211175T2 (de) 1991-02-12 1992-02-12 Sputterverfahren zum Bilden einer Aluminiumschicht auf einem gestuften Wafer

Country Status (4)

Country Link
EP (1) EP0499241B1 (de)
JP (1) JPH07109030B2 (de)
KR (1) KR100243785B1 (de)
DE (1) DE69211175T2 (de)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271137B1 (en) 1989-11-30 2001-08-07 Stmicroelectronics, Inc. Method of producing an aluminum stacked contact/via for multilayer
US6242811B1 (en) 1989-11-30 2001-06-05 Stmicroelectronics, Inc. Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature
US5658828A (en) * 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
US5472912A (en) * 1989-11-30 1995-12-05 Sgs-Thomson Microelectronics, Inc. Method of making an integrated circuit structure by using a non-conductive plug
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
EP0430403B1 (de) 1989-11-30 1998-01-07 STMicroelectronics, Inc. Verfahren zum Herstellen von Zwischenschicht-Kontakten
US6287963B1 (en) 1990-11-05 2001-09-11 Stmicroelectronics, Inc. Method for forming a metal contact
DE69319993T2 (de) * 1992-09-22 1998-12-10 Sgs Thomson Microelectronics Methode zur Herstellung eines Metallkontaktes
US5360524A (en) * 1993-04-13 1994-11-01 Rudi Hendel Method for planarization of submicron vias and the manufacture of semiconductor integrated circuits
US5356836A (en) * 1993-08-19 1994-10-18 Industrial Technology Research Institute Aluminum plug process
DE4433326A1 (de) * 1994-09-19 1996-03-21 Siemens Ag Verfahren zur planarisierenden Sputterabscheidung einer aluminiumhaltigen Schicht bei der Herstellung integrierter Schaltungen
JPH08191104A (ja) 1995-01-11 1996-07-23 Hitachi Ltd 半導体集積回路装置およびその製造方法
US6309971B1 (en) 1996-08-01 2001-10-30 Cypress Semiconductor Corporation Hot metallization process
US6045670A (en) * 1997-01-08 2000-04-04 Applied Materials, Inc. Back sputtering shield
WO1998047178A2 (en) * 1997-04-11 1998-10-22 Novellus Systems, Inc. Method and apparatus for thin film aluminum planarization
FR2769923B1 (fr) * 1997-10-17 2001-12-28 Cypress Semiconductor Corp Procede ameliore de metallisation a chaud
US6169030B1 (en) 1998-01-14 2001-01-02 Applied Materials, Inc. Metallization process and method
TWI401327B (zh) * 2010-06-23 2013-07-11 China Steel Corp 鋁薄膜製造方法
JP2012248613A (ja) * 2011-05-26 2012-12-13 Elpida Memory Inc 半導体装置の製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63162854A (ja) * 1986-12-25 1988-07-06 Fujitsu Ltd 金属膜形成方法

Also Published As

Publication number Publication date
EP0499241B1 (de) 1996-06-05
JPH07109030B2 (ja) 1995-11-22
EP0499241A1 (de) 1992-08-19
JPH0586466A (ja) 1993-04-06
DE69211175D1 (de) 1996-07-11
KR100243785B1 (ko) 2000-02-01
KR920017177A (ko) 1992-09-26

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Legal Events

Date Code Title Description
8332 No legal effect for de
8370 Indication of lapse of patent is to be deleted
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee