DE69131003T2 - Verfahren und Vorrichtung zur Umschaltung eines Frequenzsynthesierers in einen Wartezustand - Google Patents

Verfahren und Vorrichtung zur Umschaltung eines Frequenzsynthesierers in einen Wartezustand

Info

Publication number
DE69131003T2
DE69131003T2 DE69131003T DE69131003T DE69131003T2 DE 69131003 T2 DE69131003 T2 DE 69131003T2 DE 69131003 T DE69131003 T DE 69131003T DE 69131003 T DE69131003 T DE 69131003T DE 69131003 T2 DE69131003 T2 DE 69131003T2
Authority
DE
Germany
Prior art keywords
switching
waiting state
frequency synthesizer
synthesizer
waiting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69131003T
Other languages
English (en)
Other versions
DE69131003D1 (de
Inventor
David C Babin
John D Hatchett
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69131003D1 publication Critical patent/DE69131003D1/de
Publication of DE69131003T2 publication Critical patent/DE69131003T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/199—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0802—Details of the phase-locked loop the loop being adapted for reducing power consumption
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/18—Temporarily disabling, deactivating or stopping the frequency counter or divider
DE69131003T 1990-12-26 1991-12-19 Verfahren und Vorrichtung zur Umschaltung eines Frequenzsynthesierers in einen Wartezustand Expired - Fee Related DE69131003T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/633,867 US5075638A (en) 1990-12-26 1990-12-26 Standby system for a frequency synthesizer

Publications (2)

Publication Number Publication Date
DE69131003D1 DE69131003D1 (de) 1999-04-22
DE69131003T2 true DE69131003T2 (de) 1999-10-07

Family

ID=24541446

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69131003T Expired - Fee Related DE69131003T2 (de) 1990-12-26 1991-12-19 Verfahren und Vorrichtung zur Umschaltung eines Frequenzsynthesierers in einen Wartezustand

Country Status (4)

Country Link
US (1) US5075638A (de)
EP (1) EP0492433B1 (de)
JP (1) JP2841989B2 (de)
DE (1) DE69131003T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5842029A (en) * 1991-10-17 1998-11-24 Intel Corporation Method and apparatus for powering down an integrated circuit transparently and its phase locked loop
US5473767A (en) * 1992-11-03 1995-12-05 Intel Corporation Method and apparatus for asynchronously stopping the clock in a processor
KR100355837B1 (ko) * 1993-03-10 2002-10-12 내셔널 세미콘덕터 코포레이션 위상 동기 루프 및 신호발생방법
US5339278A (en) * 1993-04-12 1994-08-16 Motorola, Inc. Method and apparatus for standby recovery in a phase locked loop
US6097933A (en) * 1997-12-04 2000-08-01 Glenayre Electronics, Inc. Method and apparatus for conserving power in a pager
US7027796B1 (en) * 2001-06-22 2006-04-11 Rfmd Wpan, Inc. Method and apparatus for automatic fast locking power conserving synthesizer
US7289830B2 (en) * 2005-03-18 2007-10-30 Lear Corporation System and method for vehicle module wake up in response to communication activity
EP2041599B1 (de) * 2006-07-13 2010-09-01 Siemens Aktiengesellschaft Radaranordnung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030045A (en) * 1976-07-06 1977-06-14 International Telephone And Telegraph Corporation Digital double differential phase-locked loop
US4841255A (en) * 1987-06-24 1989-06-20 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer
GB2207309B (en) * 1987-07-11 1992-05-13 Plessey Co Plc Frequency synthesiser with provision for standby mode
US5008629A (en) * 1988-06-20 1991-04-16 Matsushita Electric Industrial Co., Ltd. Frequency synthesizer
JP2795323B2 (ja) * 1989-06-14 1998-09-10 富士通株式会社 位相差検出回路
US4968950A (en) * 1989-12-18 1990-11-06 Motorola, Inc. PLL frequency synthesizer output control circuit
US4951005A (en) * 1989-12-27 1990-08-21 Motorola, Inc. Phase locked loop with reduced frequency/phase lock time

Also Published As

Publication number Publication date
EP0492433A2 (de) 1992-07-01
EP0492433A3 (en) 1993-05-05
US5075638A (en) 1991-12-24
DE69131003D1 (de) 1999-04-22
JPH04343525A (ja) 1992-11-30
JP2841989B2 (ja) 1998-12-24
EP0492433B1 (de) 1999-03-17

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Legal Events

Date Code Title Description
8328 Change in the person/name/address of the agent

Free format text: SCHUMACHER & WILLSAU, PATENTANWALTSSOZIETAET, 80335 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC., AUSTIN, TEX., US

8339 Ceased/non-payment of the annual fee