DE69129729D1 - FIFO-Puffer - Google Patents

FIFO-Puffer

Info

Publication number
DE69129729D1
DE69129729D1 DE69129729T DE69129729T DE69129729D1 DE 69129729 D1 DE69129729 D1 DE 69129729D1 DE 69129729 T DE69129729 T DE 69129729T DE 69129729 T DE69129729 T DE 69129729T DE 69129729 D1 DE69129729 D1 DE 69129729D1
Authority
DE
Germany
Prior art keywords
fifo buffer
fifo
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69129729T
Other languages
English (en)
Other versions
DE69129729T2 (de
Inventor
Trevor Robert Fox
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Services Ltd
Original Assignee
Fujitsu Services Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Services Ltd filed Critical Fujitsu Services Ltd
Publication of DE69129729D1 publication Critical patent/DE69129729D1/de
Application granted granted Critical
Publication of DE69129729T2 publication Critical patent/DE69129729T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F2205/10—Indexing scheme relating to groups G06F5/10 - G06F5/14
    • G06F2205/102—Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Communication Control (AREA)
DE69129729T 1990-11-06 1991-09-06 FIFO-Puffer Expired - Fee Related DE69129729T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909024084A GB9024084D0 (en) 1990-11-06 1990-11-06 First-in-first-out buffer

Publications (2)

Publication Number Publication Date
DE69129729D1 true DE69129729D1 (de) 1998-08-13
DE69129729T2 DE69129729T2 (de) 1999-03-04

Family

ID=10684931

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69129729T Expired - Fee Related DE69129729T2 (de) 1990-11-06 1991-09-06 FIFO-Puffer

Country Status (6)

Country Link
US (1) US5138637A (de)
EP (1) EP0484652B1 (de)
AU (1) AU642547B2 (de)
DE (1) DE69129729T2 (de)
GB (1) GB9024084D0 (de)
ZA (1) ZA917280B (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04346538A (ja) * 1991-05-23 1992-12-02 Nec Corp セル交換機
JP2829807B2 (ja) * 1992-07-10 1998-12-02 松下電器産業株式会社 セル遅延付加回路
CA2106271C (en) * 1993-01-11 2004-11-30 Joseph H. Steinmetz Single and multistage stage fifo designs for data transfer synchronizers
FR2709857B1 (fr) * 1993-09-10 1995-10-20 Cit Alcatel Dispositif de comparaison des rythmes d'écriture et de lecture d'une mémoire-tampon.
EP0845739A1 (de) * 1996-11-29 1998-06-03 Alcatel Datenübertragungsverfahren und Gerät dafür, ein mit diesem Gerät zu gebrauchendem Vergleicher, der als Füllstandskontroller eines Speichergeräts verwendet wird
US6000022A (en) * 1997-10-10 1999-12-07 Micron Technology, Inc. Method and apparatus for coupling signals between two circuits operating in different clock domains
US6434684B1 (en) 1998-09-03 2002-08-13 Micron Technology, Inc. Method and apparatus for coupling signals across different clock domains, and memory device and computer system using same
US6240507B1 (en) 1998-10-08 2001-05-29 International Business Machines Corporation Mechanism for multiple register renaming and method therefor
EP1039371A1 (de) * 1999-03-24 2000-09-27 Motorola, Inc. Ein Gerät und eine Methode für die Behandlung von Daten zwischen zwei asynchronen Einheiten
US6546451B1 (en) * 1999-09-30 2003-04-08 Silicon Graphics, Inc. Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
EP1182543B1 (de) * 2000-08-17 2005-08-24 Texas Instruments Incorporated Unterhaltung einer entfernten Warteschlange unter Benutzung von zwei Zählern in der Verschiebesteuerung mit Hubs und Ports
US6810098B1 (en) * 2000-12-08 2004-10-26 Cypress Semiconductor Corp. FIFO read interface protocol
US6816979B1 (en) 2001-02-01 2004-11-09 Cypress Semiconductor Corp. Configurable fast clock detection logic with programmable resolution
US6696854B2 (en) 2001-09-17 2004-02-24 Broadcom Corporation Methods and circuitry for implementing first-in first-out structure
WO2011058659A1 (ja) * 2009-11-16 2011-05-19 富士通株式会社 Fifoバッファ及びfifoバッファの制御方法
US10592442B2 (en) * 2017-12-11 2020-03-17 Advanced Micro Devices, Inc. Asynchronous buffer with pointer offsets

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4393482A (en) * 1979-11-08 1983-07-12 Ricoh Company, Ltd. Shift register
JPS6057090B2 (ja) * 1980-09-19 1985-12-13 株式会社日立製作所 データ記憶装置およびそれを用いた処理装置
US4884286A (en) * 1985-12-12 1989-11-28 Texas Instruments Inc. Elastic buffer for local area networks
US4965794A (en) * 1987-10-05 1990-10-23 Dallas Semiconductor Corporation Telecommunications FIFO
US4839893A (en) * 1987-10-05 1989-06-13 Dallas Semiconductor Corporation Telecommunications FIFO
US4891788A (en) * 1988-05-09 1990-01-02 Kreifels Gerard A FIFO with almost full/almost empty flag
US5020081A (en) * 1988-09-30 1991-05-28 Data General Corporation Communication link interface with different clock rate tolerance
US5033064A (en) * 1988-12-09 1991-07-16 Transwitch Corporation Clock dejitter circuit for regenerating DS1 signal
JPH0630053B2 (ja) * 1989-02-13 1994-04-20 株式会社東芝 遅延バッファ回路
US5267191A (en) * 1989-04-03 1993-11-30 Ncr Corporation FIFO memory system

Also Published As

Publication number Publication date
AU642547B2 (en) 1993-10-21
ZA917280B (en) 1992-05-27
EP0484652A3 (en) 1993-04-21
GB9024084D0 (en) 1990-12-19
EP0484652B1 (de) 1998-07-08
DE69129729T2 (de) 1999-03-04
EP0484652A2 (de) 1992-05-13
AU8701091A (en) 1992-05-14
US5138637A (en) 1992-08-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee