DE69127874D1 - Signalweglenkung für aufeinandergestapelte Multiprozessormodule - Google Patents

Signalweglenkung für aufeinandergestapelte Multiprozessormodule

Info

Publication number
DE69127874D1
DE69127874D1 DE69127874T DE69127874T DE69127874D1 DE 69127874 D1 DE69127874 D1 DE 69127874D1 DE 69127874 T DE69127874 T DE 69127874T DE 69127874 T DE69127874 T DE 69127874T DE 69127874 D1 DE69127874 D1 DE 69127874D1
Authority
DE
Germany
Prior art keywords
signal routing
stacked multiprocessor
multiprocessor modules
modules
stacked
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127874T
Other languages
English (en)
Other versions
DE69127874T2 (de
Inventor
John Maurice Segelken
Richard Robert Shively
Christopher Anthony Stanziola
Lesley Jen-Yuan Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
AT&T Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Corp filed Critical AT&T Corp
Application granted granted Critical
Publication of DE69127874D1 publication Critical patent/DE69127874D1/de
Publication of DE69127874T2 publication Critical patent/DE69127874T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/023—Stackable modules
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Multi Processors (AREA)
DE69127874T 1990-09-28 1991-07-19 Signalweglenkung für aufeinandergestapelte Multiprozessormodule Expired - Fee Related DE69127874T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/590,246 US5420754A (en) 1990-09-28 1990-09-28 Stacked board assembly for computing machines, including routing boards

Publications (2)

Publication Number Publication Date
DE69127874D1 true DE69127874D1 (de) 1997-11-13
DE69127874T2 DE69127874T2 (de) 1998-02-05

Family

ID=24361464

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127874T Expired - Fee Related DE69127874T2 (de) 1990-09-28 1991-07-19 Signalweglenkung für aufeinandergestapelte Multiprozessormodule

Country Status (4)

Country Link
US (1) US5420754A (de)
EP (1) EP0478121B1 (de)
JP (1) JPH077320B2 (de)
DE (1) DE69127874T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9117148D0 (en) * 1991-08-08 1991-09-25 Skimming William G 3-dimensional modular processing engine
US6421251B1 (en) * 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US20040115995A1 (en) * 2002-11-25 2004-06-17 Sanders Samuel Sidney Circuit array module
US9471535B2 (en) 2012-04-20 2016-10-18 International Business Machines Corporation 3-D stacked multiprocessor structures and methods for multimodal operation of same
US9391047B2 (en) 2012-04-20 2016-07-12 International Business Machines Corporation 3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of configuration parameters
US9569402B2 (en) 2012-04-20 2017-02-14 International Business Machines Corporation 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components
US8799710B2 (en) 2012-06-28 2014-08-05 International Business Machines Corporation 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits
US9257152B2 (en) 2012-11-09 2016-02-09 Globalfoundries Inc. Memory architectures having wiring structures that enable different access patterns in multiple dimensions
US9195630B2 (en) 2013-03-13 2015-11-24 International Business Machines Corporation Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure
US9383411B2 (en) 2013-06-26 2016-07-05 International Business Machines Corporation Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers
US9336144B2 (en) 2013-07-25 2016-05-10 Globalfoundries Inc. Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations
US9389876B2 (en) 2013-10-24 2016-07-12 International Business Machines Corporation Three-dimensional processing system having independent calibration and statistical collection layer
US10993323B2 (en) 2019-01-14 2021-04-27 Cody Elsing Stackable printed circuit board
GB201904267D0 (en) 2019-03-27 2019-05-08 Graphcore Ltd A networked computer with multiple embedded rings
US11704270B2 (en) 2019-03-27 2023-07-18 Graphcore Limited Networked computer with multiple embedded rings
CN110337178B (zh) * 2019-04-25 2021-03-23 维沃移动通信有限公司 一种电路板组件和电子设备

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1356632A (en) * 1971-07-09 1974-06-12 Plessey Co Ltd Multiplayer printed-circuit boards
US4739474A (en) * 1983-03-10 1988-04-19 Martin Marietta Corporation Geometric-arithmetic parallel processor
EP0213205B1 (de) * 1984-12-28 1992-12-09 Micro Co., Ltd. Stapelverfahren für gedruckte schaltungen
US5038386A (en) * 1986-08-29 1991-08-06 International Business Machines Corporation Polymorphic mesh network image processing system
US5058001A (en) * 1987-03-05 1991-10-15 International Business Machines Corporation Two-dimensional array of processing elements for emulating a multi-dimensional network
US4891751A (en) * 1987-03-27 1990-01-02 Floating Point Systems, Inc. Massively parallel vector processing computer
US4953005A (en) * 1987-04-17 1990-08-28 Xoc Devices, Inc. Packaging system for stacking integrated circuits
GB2206452B (en) * 1987-06-23 1991-01-09 Burr Brown Ltd Printed circuit board topography for high speed intelligent industrial controller
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4967314A (en) * 1988-03-28 1990-10-30 Prime Computer Inc. Circuit board construction
US4907128A (en) * 1988-12-15 1990-03-06 Grumman Aerospace Corporation Chip to multilevel circuit board bonding
US5020059A (en) * 1989-03-31 1991-05-28 At&T Bell Laboratories Reconfigurable signal processor
US5089880A (en) * 1989-06-07 1992-02-18 Amdahl Corporation Pressurized interconnection system for semiconductor chips

Also Published As

Publication number Publication date
EP0478121B1 (de) 1997-10-08
US5420754A (en) 1995-05-30
EP0478121A3 (en) 1992-04-15
EP0478121A2 (de) 1992-04-01
JPH0527871A (ja) 1993-02-05
JPH077320B2 (ja) 1995-01-30
DE69127874T2 (de) 1998-02-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee