DE69127182T2 - Mehrfachbefehlausgabe - Google Patents

Mehrfachbefehlausgabe

Info

Publication number
DE69127182T2
DE69127182T2 DE69127182T DE69127182T DE69127182T2 DE 69127182 T2 DE69127182 T2 DE 69127182T2 DE 69127182 T DE69127182 T DE 69127182T DE 69127182 T DE69127182 T DE 69127182T DE 69127182 T2 DE69127182 T2 DE 69127182T2
Authority
DE
Germany
Prior art keywords
command issue
multiple command
issue
command
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69127182T
Other languages
English (en)
Other versions
DE69127182D1 (de
Inventor
Saeid Azmoodeh
Peter Malcolm Keith Boffey
Richard Matthew Forsyth
Brian Jeremy Parsons
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd Great Britain
Original Assignee
SGS Thomson Microelectronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd filed Critical SGS Thomson Microelectronics Ltd
Application granted granted Critical
Publication of DE69127182D1 publication Critical patent/DE69127182D1/de
Publication of DE69127182T2 publication Critical patent/DE69127182T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
DE69127182T 1990-12-21 1991-12-18 Mehrfachbefehlausgabe Expired - Fee Related DE69127182T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB909027853A GB9027853D0 (en) 1990-12-21 1990-12-21 Multiple instruction issue

Publications (2)

Publication Number Publication Date
DE69127182D1 DE69127182D1 (de) 1997-09-11
DE69127182T2 true DE69127182T2 (de) 1998-03-12

Family

ID=10687473

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69127182T Expired - Fee Related DE69127182T2 (de) 1990-12-21 1991-12-18 Mehrfachbefehlausgabe

Country Status (5)

Country Link
US (1) US5742783A (de)
EP (1) EP0492968B1 (de)
JP (1) JP3100721B2 (de)
DE (1) DE69127182T2 (de)
GB (1) GB9027853D0 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69327688T2 (de) * 1992-08-12 2000-09-07 Advanced Micro Devices Inc Befehlsdecoder
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism
US5481743A (en) * 1993-09-30 1996-01-02 Apple Computer, Inc. Minimal instruction set computer architecture and multiple instruction issue method
US5958042A (en) * 1996-06-11 1999-09-28 Sun Microsystems, Inc. Grouping logic circuit in a pipelined superscalar processor
US5898852A (en) * 1997-06-26 1999-04-27 Sun Microsystems, Inc. Load instruction steering in a dual data cache microarchitecture
US6115807A (en) * 1997-12-19 2000-09-05 Intel Corporation Static instruction decoder utilizing a circular queue to decode instructions and select instructions to be issued
US6742110B2 (en) * 1998-10-06 2004-05-25 Texas Instruments Incorporated Preventing the execution of a set of instructions in parallel based on an indication that the instructions were erroneously pre-coded for parallel execution
JP3841967B2 (ja) 1999-01-19 2006-11-08 株式会社ルネサステクノロジ マイクロプロセッサ
US6336182B1 (en) * 1999-03-05 2002-01-01 International Business Machines Corporation System and method for utilizing a conditional split for aligning internal operation (IOPs) for dispatch
US6304959B1 (en) 1999-03-05 2001-10-16 International Business Machines Corporation Simplified method to generate BTAGs in a decode unit of a processing system
US6425069B1 (en) 1999-03-05 2002-07-23 International Business Machines Corporation Optimization of instruction stream execution that includes a VLIW dispatch group
JP4025493B2 (ja) 2000-08-08 2007-12-19 富士通株式会社 適切な発行先に命令を発行する命令発行装置
JP4272371B2 (ja) * 2001-11-05 2009-06-03 パナソニック株式会社 デバッグ支援装置、コンパイラ装置、デバッグ支援プログラム、コンパイラプログラム、及びコンピュータ読取可能な記録媒体。
KR101412885B1 (ko) * 2012-03-26 2014-06-26 서울대학교산학협력단 모드 설정 및 구분자를 이용하여 저장 매체에서의 영속화를 제어하는 방법 및 그 스토리지 시스템
US9710278B2 (en) * 2014-09-30 2017-07-18 International Business Machines Corporation Optimizing grouping of instructions
KR102051206B1 (ko) * 2018-01-23 2019-12-02 연세대학교 산학협력단 내포된 루프 구조를 포함하는 프로그램을 위한 컴파일 장치 및 방법과 이에 관한 기록매체
US10996952B2 (en) 2018-12-10 2021-05-04 SiFive, Inc. Macro-op fusion
CN111857830B (zh) * 2020-06-05 2023-09-22 上海赛昉科技有限公司 一种提前转发指令数据的通路设计方法、系统及存储介质

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4128880A (en) * 1976-06-30 1978-12-05 Cray Research, Inc. Computer vector register processing
JPS6028015B2 (ja) * 1980-08-28 1985-07-02 日本電気株式会社 情報処理装置
US4847755A (en) * 1985-10-31 1989-07-11 Mcc Development, Ltd. Parallel processing method and apparatus for increasing processing throughout by parallel processing low level instructions having natural concurrencies
US4903196A (en) * 1986-05-02 1990-02-20 International Business Machines Corporation Method and apparatus for guaranteeing the logical integrity of data in the general purpose registers of a complex multi-execution unit uniprocessor
US4890218A (en) * 1986-07-02 1989-12-26 Raytheon Company Variable length instruction decoding apparatus having cross coupled first and second microengines
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5293500A (en) * 1989-02-10 1994-03-08 Mitsubishi Denki K.K. Parallel processing method and apparatus
US5197137A (en) * 1989-07-28 1993-03-23 International Business Machines Corporation Computer architecture for the concurrent execution of sequential programs
US5203002A (en) * 1989-12-27 1993-04-13 Wetzel Glen F System with a multiport memory and N processing units for concurrently/individually executing 2N-multi-instruction-words at first/second transitions of a single clock cycle
JP2818249B2 (ja) * 1990-03-30 1998-10-30 株式会社東芝 電子計算機
EP0454985B1 (de) * 1990-05-04 1996-12-18 International Business Machines Corporation Maschinenarchitektur für skalaren Verbundbefehlssatz
US5214763A (en) * 1990-05-10 1993-05-25 International Business Machines Corporation Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism

Also Published As

Publication number Publication date
DE69127182D1 (de) 1997-09-11
JPH06342371A (ja) 1994-12-13
EP0492968A3 (en) 1994-11-30
GB9027853D0 (en) 1991-02-13
JP3100721B2 (ja) 2000-10-23
EP0492968B1 (de) 1997-08-06
EP0492968A2 (de) 1992-07-01
US5742783A (en) 1998-04-21

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee