DE69120794T2 - Spreading packet communication system - Google Patents

Description

The present invention relates generally to a satellite packet communication system and, more particularly, to a spread packet communication system.

The slotted and unslotted ALOHA packet communication systems (ALOHA packet communication systems with and without fixed time protection) are well known. In these systems, connecting stations with a very small opening angle (VSAT stations) randomly transmit their data packets in the form of data bundles (bursts) via a satellite transponder to a central station. A modified version of the ALOHA system is the spread ALOHA network, proposed by Norman Abramson in 1986 and described in "Spread ALOHA for VSAT Networkstl₁ Norman Abramson, Technical Report B86-4b, University of Hawaii, June 1986 (rev. 1/87). According to this technique, packet data from each VSAT station is spread, or "spread," over the time domain using an encoded sequence of pseudorandom numbers to reduce the probability of burst collisions and to reduce the transmission power per bit. Two spreading methods are known. One is the bit-spread ALOHA system, in which each data bit is spread into several pseudorandom code bits, and the other is the chip-spread ALOHA system, in which each pseudorandom code bit (or chip) is spread with the data bits of a packet. Implementations of the The spread ALOHA system proposed by , have not yet been manufactured due to the expected difficulties with the hardware of the central station demodulator system, which must be synchronized with high speed chip rate clock pulses in order to detect correlations between received data bits and a pseudorandom number (PN) sequence (see also: Proceedings of the IEEE, Volume 78, No. 7, July 1990, New York, US, pages 1267-1274; N. Abramson: "VSAT Data Network").

It is therefore an object of the present invention to provide a spread packet communication system that simplifies the hardware of its central station facility. This object is solved with the features of the claims.

The described satellite packet communication system has a central station which generates chip rate clock pulses and transmits a series of data in time slots of a frame to a satellite transponder, and several connection stations. Each connection station receives the frame from the transponder and recovers the chip rate clock pulses from the received frame. The connection station contains a pseudorandom number sequence generator (PN sequence generator) synchronized with the recovered chip rate clock pulses for generating bits of a PN sequence with which packed data bits are pseudorandomly modulated and transmitted in burst form to the transponder. The central station contains a correlator synchronized with the central station chip rate clock pulses to detect correlations between the pseudorandom number modulated data bits and a sequence of pseudorandom numbers corresponding to the PN sequence bits of the connecting stations.

The simplification of the bit-spread packet hardware is achieved by recovering the chip rate clock pulses from the data rate of a received frame signal at each terminal station. In particular, the central station of a bit-spread packet communication system generates chip rate clock pulses, derives data rate clock pulses from the chip rate clock pulses, and transmits a series of data synchronously with the data rate clock pulses to a satellite transponder in time slots of a frame. Each terminal station includes a data rate clock recovery circuit for recovering data rate clock pulses from the frame signal received from the transponder and a chip rate clock recovery circuit for recovering the chip rate clock pulses from the recovered data rate clock pulses to synchronize the pseudorandom number sequence (PN) generator.

In order to take into account the different connection To compensate for propagation delays, the central station receives its own frame signal from the transponder and recovers the data rate clock pulses from the received frame. A first chip rate clock recovery circuit recovers chip rate clock pulses from the recovered data rate clock pulses and a second chip rate clock recovery circuit is provided for recovering chip rate pulses from an output signal of the correlator. A phase detector is connected to the first and second chip rate clock recovery circuits to detect a phase difference between their output signals and a signal indicative of the detected phase difference is transmitted to the transponder in a time slot. Each terminal station receives the phase difference signal in an assigned time slot and controls the phase position of the chip rate clock pulses sent to the PN sequence generator in accordance with the phase difference signal.

To minimize interference caused by burst collisions, each terminal station cyclically shifts the PN sequence generator by k bits, where k is in the range between 1 and m-1, where m is the number of bits in the PN sequence. Packed data bits from each terminal station are synchronized with the recovered data bit clock pulses. The central station correlator contains 2xm multipliers divided into a first and a second group, with the multipliers of each group having m pseudorandom numbers. The k value of each terminal station is different from the k value of the other terminal stations.

The hardware simplification for chip spread packets is achieved by recovering the chip rate clock pulses from the start time of a received frame signal at each terminal station. In particular, the central station generates chip rate clock pulses corresponding to time slots of a frame and transmits a series of data in the time slots to a satellite transponder. Each terminal station receives the frame from the transponder, detects the start time of the received frame, and recovers the chip rate clock pulses from the detected frame start time. to synchronize the PN sequence generator.

The present invention will be described in more detail with reference to the accompanying drawings, in which:

Fig. 1 is a block diagram of an ALOHA bit-spread satellite communication system according to a first embodiment of the present invention;

Fig. 2 is a waveform diagram associated with Fig. 1;

Fig. 3 is a block diagram of an ALOHA bit-spread satellite communication system according to a second embodiment of the present invention;

Fig. 4 is a block diagram of an ALOHA bit-spread satellite communication system according to a third embodiment of the present invention;

Figures 5A and 5B are illustrations of the colliding data bit streams associated with Figure 4;

Fig. 6 is a block diagram of an ALOHA spread chip satellite communication system of the present invention; and

Fig. 7 is a waveform diagram associated with Fig. 6.

Referring now to Fig. 1, there is shown a spread ALOHA communication system according to an embodiment of the present invention. The system comprises a central station 1 and a plurality of VSAT (very small aperture terminal) stations 2-1 through 2-N connected to the central station via a satellite transponder 30.

The central station 1 has a chip rate clock generator 18 which sends 256 kbps chip rate clock pulses to a data rate clock generator 16. The data rate clock generator 16 divides the frequency of the chip rate clock pulses by a factor of 64 and sends a 4 kbps data rate clock pulse to a multiplexer 10 in which 4 kbps transmit data is multiplexed with frame sync codes. The multiplexed signal is sent to an M-stage PSK (phase shift keyed) modulator 11 where it is digitally modulated onto a carrier. The output of the PSK modulator 11 is coupled to an upconverter 12 in which the PSK modulated signal is converted to an uplink frequency of the satellite and via a high power amplifier 13 and a diplexer 14 to the central station antenna 15 to be transmitted to the satellite transponder 30.

A signal from each VSAT station is transmitted in burst form (packet form) to the transponder 30 and received at the central station by antenna 15 and sent via diplexer 14 and low noise amplifier 19 to a down converter 20 where it is converted to a baseband frequency and sent to a correlator 21. The correlator 21 includes a branched delay line 22 which is clocked by the chip rate clock generator 18 to sequentially shift the PSK modulated bit stream to the chip rate of 256 kbps. Successive branches of delay line 22 are respectively coupled to multipliers 23-1 through 23-m, each set to different values (+1 and -1) corresponding to bits of a pseudorandom number sequence by which the original packet data bits of each modub 2 VSAT station have been summed or "spread." The outputs of multipliers 23 are summed by an adder 24 for coupling to a PSK demodulator 25.

The frame signal from the central station 1 is retransmitted by the transponder 30 to all VSAT stations in a broadcast mode. Each VSAT station receives the broadcast signal by antenna 40 and sends it via a diplexer 41 and a low noise amplifier 42 to a down converter 43 where it is converted to a baseband frequency 43. The output of the down converter 43 is coupled to a PSK demodulator 44 to which a data rate clock recovery circuit 45 is coupled to recover the data rate clock pulse. The recovered data rate clock is sent to a demultiplexer 52 to demultiplex the output of the PSK demodulator into frame syncs and data inserted in the time slot assigned to the VSAT station. The output of the data rate clock recovery circuit 45 is sent to a chip rate clock recovery circuit 46 which recovers the original 256 kbps chip rate clock by multiplying the recovered Data rate clock frequency with a factor of 64.

The output of the chip rate clock recovery circuit 46 is sent to a pseudorandom number sequence generator (PN sequence generator) 47 to drive it at the chip rate to generate an m-bit wide pseudorandom number sequence specified for all VSAT systems of the satellite communication system. The output of the PN sequence generator 47 is sent to one input of an exclusive OR gate 48. Transmit packet data is sent to the other input of the exclusive OR gate 48 where each data bit is summed with the PN sequence by modub 2.

As shown schematically in Fig. 2, a portion of the packet data represented by a series of "10110" bits is summed with a modulo 2 PN sequence, which for convenience is represented as a sequence "11010010" with a chip clock rate eight times higher than the data bit rate. As a result of the modulo 2 summation, each data bit "1" of a packet is converted into a sequence of reciprocals of the 8-bit PN sequence and each data bit "0" is converted into a bit sequence with the same bit pattern as the 8-bit PN sequence.

The spread bit stream is sent to a PSK modulator 49 where it is used to modulate a burst carrier, the modulated burst carrier being converted to an uplink frequency by an upconverter 50. After high power amplification by an amplifier 51, the uplink signal from the VSAT station is sent via the diplexer 41 to the antenna 40 for transmission to the central station 1 via the transponder 30.

At the central station, the PSK-modulated carrier burst appears at the downconverter 20 and is input to the correlator 21 where it is shifted at the chip rate along the branched delay line 22, multiplied by the random number values listed above by the multipliers 23-1 to 23-m in sequence, and the outputs of the multipliers 23 are summed by the adder 24. The adder 24 produces a positive peak value corresponding to an original data bit having a binary "1" value or a negative peak value corresponding to an original data bit having a binary "0" value each time there is a match between the m-bit wide pattern of the bit-spread PSK modulated signal and the bit pattern of the multipliers 23. Such peak values occur periodically at the data rate of 4 kbps and are demodulated into the original packet data by the PSK demodulator 25.

Since the chip rate clock of each VSAT station is synchronized with the 256 kbps reference clock of the central station, the bit-spread packet data of all VSAT stations is synchronized with the reference clock. Because of this synchronization, the correlator 21 is able to detect the original data bit stream of each packet in synchronization with the common chip rate clock, thus eliminating the need for a high-speed chip rate clock generator and complicated hardware that would otherwise be required to quickly establish synchronization with each incoming burst.

Since the VSAT stations are located at different locations, their propagation delays differ from each other to such an extent that a phase difference of less than one chip clock interval occurs within the packets arriving at the central station.

The embodiment of Fig. 3 eliminates the phase difference problem. The central station is provided with an interrogation circuit 66 which periodically sends an interrogation signal via the transponder 30 to each VSAT station to obtain a response from it. A PSK demodulator 60 is connected to the output of the down converter 20 to receive and demodulate the central station interrogation signal returning from the transponder 30 and sends it to a clock recovery circuit 61 where the data rate clock component of the returning signal is detected and fed to a chip rate clock recovery circuit 62. The latter recovers the chip rate clock time and sends it as a reference phase to a phase detector 63. Another Chip rate clock recovery circuit 64 is connected to the output of PSK demodulator 25 to recover the chip rate clock time from a response signal transmitted by the interrogated VSAT station. The output of chip rate clock recovery circuit 64 is sent to phase detector 63 for comparison with the reference phase. Phase detector 63 produces a phase difference signal corresponding to the deviation of the propagation delay of the given VSAT station from that of the central station. An encoded signal indicative of the detected phase difference is produced by encoder 65. Upon receiving a signal from interrogation circuit 66 identifying the interrogated VSAT station, encoder 65 sends the encoded phase difference signal to multiplexer 10 for transmission in a time slot assigned to the interrogated station.

Each VSAT station is connected to an interrogation transceiver 67 and a decoder 68, both of which are connected to the demultiplexer 52. The interrogation signal from the central station is fed to the interrogation transceiver 67. Upon receiving it, the transceiver 67 sends a response signal to the exclusive OR gate 48 to have it spread with the PN sequence for transmission to the central station. On the other hand, the encoded phase difference signal from the central station is demultiplexed and sent to the decoder 68 of the interrogated VSAT station. A phase shifter 69 is connected between the output of the chip rate clock recovery circuit 46 and the PN sequence generator 47. The phase shifter 69 receives the output of the decoder 68 to delay the chip rate clock pulses by an amount equal to the propagation delay difference of the own VSAT station with respect to the reference time. Therefore, the chip rate clock pulses of all VSAT stations are individually adjusted at periodic time intervals to compensate for their chip rate phase time differences.

Fig. 4 shows a third embodiment of this invention. Before describing this embodiment, it is appropriate to describe the resistance of the spread ALOHA system to interference when two Packets from the VSAT stations of different systems are transmitted simultaneously. Suppose that the VSAT station 72-1 sends a data bit sequence Ai (with i=1, 2, 3...) and the VSAT station 73-1 transmits data bits Bi. The data bit of each VSAT station is spread with a pseudorandom bit sequence X₁, X₂,...,Xm so that their transmitted sequences are represented by AiX₁, AiX₂,...AiXm and BjX₁, BjX₂,...BjXm. It is further assumed that there is a collision between these spread bit sequences so that the sequence AiX₁, AiX₂,...AiXm overlaps (mk) bits of the sequence BjX₁, BjX₂,...BjXm and k bits of the next sequence Bj+1X₁, Bj+1X₂,...Bj+1Xm as shown in Fig. 5A (where k is in the range between 1 and m-1). Since the correlator of the central station 71-1 is synchronized with the bit sequence AiX₁, AiX₂,...AiXm, the following correlation output is generated by the generator:

The first term of equation (1) corresponds to the component that is desired and the second term corresponds to the component that is produced as a result of the interference. If the autocorrelation coefficient of the PN sequence X at delay time "i" is represented by Ci, the latter is a maximum value when i=0 and is much smaller than the maximum value when i≠0. For example, if the X sequence is a maximum length sequence, Ci=m for i=0 and Ci =1 for i≠0. By rearranging equation (1) using the notation Ci, the following equations result when Bj=Bj+1:

y(t)=AiC₀+BjCk (2)

and if Bj≠bj+1:

The second term of equation (2) is significantly smaller than the first term of equation (1) and therefore the data bit sequence Ai can be received correctly. However, the second term of equation (3) cannot be minimized.

To minimize the second term of equation (3), each VSAT station is provided with a pattern shifter 70 which sends a control signal to the PN sequence generator 47 to periodically and/or randomly shift its u bit wide PN sequence by k bits. For example, if one VSAT station has the PN sequence of Fig. 2 (i.e., "11010010"), the PN sequence of another VSAT station is shifted as sequence "10100101". A shift register 72 is connected to the data input of an exclusive-OR gate 48 to store transmit packet data and send it to the exclusive-OR gate 48 in response to the output of the data rate clock recovery circuit 45. In this way, the transmit data bit timing of each VSAT station is synchronized with other VSAT stations.

The central station is provided with a correlator 73 with a branched delay line 74 having twice as many delay units as those of the branched delay line of the previous embodiments. Also, twice as many multipliers 751 to 75m are provided as those of the correlator 21 of the previous embodiments. The multipliers 751 to 75m are similarly divided into a first group of multipliers 751 to 75m and a second group of multipliers 75m+1 to 752m, and the multipliers of each group are set with the same PN sequence X1,X2...Xm.

Suppose there is a collision between the bit sequence AiX₁,AiX₂,...AiXm from the VSAT station 2-1 and a bit sequence BjX1+k,BjX2+k,...BjXm,...BjXk from the VSAT station 2-2. Since the bit sequence Bj is shifted by k bits with respect to the bit sequence Ai and the data bit timing of both packets is aligned with each other as shown in Fig. 5B, the bit sequence Ai adjusts its PN sequence which is set at the multipliers 75₁ to 75m.

The correlator 73 generates an output signal z(t) from the adder 76 for the bit sequence Ai, which is given as follows:

Since z(t) is equal to y(t) of equation (2), the interference caused by colliding packets can be kept to a minimum and the bit sequence Ai can be received correctly. Following the detection of the bit sequence Ai, the bit sequence Bj adapts its PN sequence₁ which is set at the multipliers 75k+1 to 75k+m.

While embodiments have been mentioned in which each data bit is spread with an m-bit wide PN sequence whose clock rate is higher than the data clock rate, the present invention could equally well be used for applications in which, using a smaller chip clock rate than the data clock rate, the binary levels of all data bits of each packet are randomly reversed or not depending on the binary level of each bit of a spreading PN bit sequence. As shown in Fig. 6, the central station is provided with a time base 80 for sending reference clock pulses to a chip rate clock generator 81 as well as to a data rate clock generator 16. The chip rate clock generator 81 converts the frequency of the reference clock to a lower frequency corresponding to the slot time of the frame signal and causes the correlator 21 to synchronize with the time slot frequency.

On the other hand, each VSAT station has a chip rate clock recovery circuit 82 that receives frame sync from the demultiplexer 52 to recover the original chip rate clock for driving a PN sequence generator 83 at the chip rate, i.e., the time slot frequency. The PN sequence is a maximum length sequence with a period covering several time slots. Fig. 7 shows only a portion of the PN sequence. This PN sequence is modulo-2 summed with transmit data bits by an exclusive OR gate 48 to produce the packet spread data bits shown in Fig. 7.

The foregoing description shows only preferred embodiments of the present invention. Various modifications will be apparent to those skilled in the art without departing from the scope of the present invention, which is limited only by the appended claims. Therefore, the embodiments shown and described are only illustrative, not restrictive.

Claims (4)

1. Satellite packet communication system with a central station (1) and several connecting stations (2) a) wherein the central station (1) comprises: a1) clock pulse generating devices (16,18) for generating chip rate clock pulses and for generating data rate clock pulses from the chip rate clock pulses, a2) upconverter means (11,12,13) for transmitting a series of data in time slots of a frame to a satellite transponder (30), downconverter means (19,20) for receiving a carrier burst via the transponder, a3) correlator devices (21; 73) connected to the downconverter (19, 20) for detecting correlations between pseudorandomly modulated data bits of a received carrier burst and a sequence of pseudorandom numbers, and a4) a digital demodulator (25) connected to the correlator means (21; 73) for demodulating the detected correlations to produce a copy of the packed data bits, and b) wherein each connection station (2) comprises: b1) down-converter means (42,43,44) for receiving the frame from the transponder, b2) clock recovery means (45,46) for recovering the chip rate clock pulse from the received frame, b3) a pseudorandom number sequence generator (PN sequence generator) (47) synchronized with the recovered chip rate clock pulses for generating bits of a PN sequence, b4) a pseudorandom modulator (48) connected to the PN sequence generator (47) to pseudorandomly modulate the packed data bits with the PN sequence bits, b5) a digital modulator (49) connected to the pseudorandom modulator (48) for modulating the pseudorandomly modulated packed data bits onto a burst trigger for transmission to the transponder (30), and b6) upconverter means (50,51) for transmitting a modulated carrier burst to the transponder, characterized. c) that the central station (1) has a multiplexer (10) for multiplexing the data rate clock pulses with the data, d) that the correlator devices (21; 73) of the central station are synchronized with the chip rate clock pulses generated by the clock pulse generating device (18) in order to detect correlations, and e) that the clock recovery devices (45,46) of each connection station have the following: e1) a data rate clock recovery device (45) for detecting the data rate clock pulses which are multiplexed with the transmitted data, and e2) a chip rate clock recovery device (46) for recovering the chip rate clock pulses from the data rate clock pulses detected by the data rate clock recovery device (45). 2. System according to claim 1, characterized in that the central station (1) comprises: a) a data rate recovery circuit (61) for recovering the chip rate clock pulses from the carrier burst from each connecting station; b) a first chip rate clock recovery circuit (62) for recovering the chip rate clock pulses from the recovered data rate clock pulses; c) a second chip rate clock recovery circuit (64) for recovering the chip rate clock pulses from an output signal of the correlator device (21); d) means (63) for detecting a phase difference between the chip rate clock pulses recovered by the first chip rate clock recovery circuit (62) and the chip rate clock pulses recovered by the second chip rate clock recovery circuit (64) and for transmitting a signal indicating the detected phase difference in a time slot of the transponder (30), e) that each terminal station has means (52,68,69) for receiving the phase difference signal in an assigned time slot and for controlling the phase position of the PN sequence generator (47) according to the phase difference signal. 3. System according to claim 2, characterized in a) that the central station (1) further comprises an interrogation transmitter (66) for periodically transmitting an interrogation signal to each connecting station (2) via the transponder, b) that each connection station (2) has an interrogation transceiver (67) to receive the interrogation signal addressed to the connection station and to send a return signal to the pseudorandom modulating device (48) to transmit it to the central station in response to the addressed interrogation signal, and c) that the data rate clock recovery circuit (61) receives the interrogation signal to derive the data rate clock pulses. 4. A system according to claim 1, 2 or 3, characterized in that the PN sequence of each terminal is an m-bit wide sequence, and each terminal provides a burst transmission on a random basis and comprises: means (70) for cyclically shifting the PN sequence generator (47) by k bits, where k is in the range between 1 and m-1 and the integer k is different for each terminal; and a device (72) which synchronizes the packed data bits with the recovered data bit clock pulses, that the correlator device (73) of the central station has the following: a branched delay line (74) clocked with the chip rate clock pulses generated by the clock recovery means (18) to receive an output signal from the down converter means (19,20); 2xm multipliers (75) each coupled to successive branches of the branched delay line, the multipliers being divided into a first group of m pseudorandom numbers and a second group of m pseudorandom numbers and an adder (76) for summing output signals of the 2xm multipliers to produce a summed output signal as correlations.