DE69030853T2 - GRADED RECORDING PRINTER - Google Patents

Description

Field of the invention

The present invention relates to a printer for gradation recording by the electrophotographic system.

Background of the invention

A printer uses the electrophotographic system to produce print patterns through exposure of light-sensitive material and development and fixing processes.

As a printer of the electrophotographic system, an LED printer has been proposed in which a plurality of LED elements are used to expose photosensitive material, and these are individually controlled depending on printing patterns.

Compared with a laser printer, the LED printer is characterized in that a solid-state scanning system is used and no mechanical main scanning is required, the overall size of the device can also be reduced since an optical system can be formed in a small size, and progress in semiconductor technology has realized low cost.

However, a plurality of LED elements leads to a fluctuation of the optical intensity depending on the LED element.

In order to compensate for such fluctuation of optical intensity, as proposed in Japanese Patent Laid-Open No. 58-78476, for example, the light emission period given to each LED element is changed to equalize the light emission intensity of each LED element.

Traditionally, gradation recording in the LED printer was carried out by changing the light emission period of each LED element.

However, as already explained, a plurality of LED elements creates a fluctuation in the light intensity for each LED element, and thereby the recording spot size of each LED element creates a fluctuation.

Consequently, a problem arises that a certain single LED element, regardless of smaller gradation data to be recorded, emits a higher amount of light than that of the adjacent LED elements, the so-called inverse gradation phenomenon is generated, gradation cannot be expressed accurately, and thereby the print quality may be deteriorated.

Therefore, for example, Japanese Patent Laid-Open No. 62-284567 proposes an LED printer that ensures proper concentration gradation by correcting the fluctuation of light intensity of LED elements.

However, this LED printer requires an increase in the number of light emission pulses per each recording pixel in response to an increase in the number of gradation expressions and accuracy of correction of fluctuation, and thereby creates a problem that a memory capacity becomes extremely large.

Accordingly, in view of such problems of the prior art, an object of the present invention is to provide an LED printer which realizes expression of accurate gradation without increasing the memory capacity.

US-A-4,855,760 discloses an image forming method and an image forming apparatus in which current supply time periods for light emitting diodes constituting a light emitting diode array are controlled according to gradation levels while a constant current is supplied to the light emitting diodes, and the current supply time period at each gradation level is adjusted according to variations in the light intensity of the light emitting diodes when the constant current is supplied, thereby correcting the variations in the light output intensities of the light emitting diodes. The apparatus includes means for holding gradation information concerning the individual light emitting diodes, means for holding correction information for correcting variations in light intensity characteristics between the individual light emitting diodes, and control means for controlling the individual light emitting diodes to emit light during time periods depending on the gradation information and the correction information. In this device, each light emitting diode is continuously controlled to be ON for a number of periods depending on the gradation information for the diode concerned, as set by the correction information for that diode.

Disclosure of the invention

According to the present invention, there is provided an electrophotographic printer comprising

a linear arrangement of a plurality of individual recording elements,

Means for holding gradation information concerning the individual recording elements of the plurality,

means for holding correction information for correcting variations in the light intensity characteristics between the individual recording elements of the plurality, and

Control means for controlling the individual recording elements of the plurality to emit light for periods of time depending on the gradation information and the correction information,

marked by

Enable means for providing successive enable signals of different respective durations to the control means, which control means are enabled to control the individual recording elements to emit light only for enabled periods of the duration of the successive enable signals, whereby light emissions from the individual recording elements in different enable periods according to the durations of those periods are weighted differently,

Selection means operable to select for each individual recording element of the plurality and for each of the successive enabling periods of the control means whether the respective recording element is to be controlled to emit light in the respective enabling period in dependence on the gradation information and the correction information.

According to the electrophotographic printer of the present invention, it is possible to use a smaller amount of information because of the weighted light emission pattern signals, whereby a smaller amount of gradation information and fluctuation correction information to be expressed is required and the memory capacity can also be reduced.

Short description of the drawings

Fig. 1 is a diagram for explaining a structure of an LED printer,

Fig. 2 is a diagram for explaining a structure of an LED head,

Fig. 3 is a diagram for explaining a structure of an embodiment,

Fig. 4 is a diagram for explaining control timing signals of an embodiment,

Fig. 5 is a diagram for explaining a light quantity correction ROM,

Fig. 6 is a diagram for explaining the conversion operation of an LED light pattern,

Fig. 7 is a diagram for explaining another embodiment,

Fig. 8 is a diagram for explaining control timing signals of another embodiment, and

Fig. 9 is a diagram for explaining a light amount correction ROM in another embodiment.

Preferred embodiment of the invention

The present invention will be explained in detail with reference to the accompanying drawings.

Fig. 1 is a diagram for explaining a structure of an LED printer. A photosensitive drum 10, which is formed as an image carrier for carrying an electrostatic latent image of a continuous type, is charged to a uniform potential (for example, -600 V) on the surface thereof by a precharger 11 such as a corona discharger, and thereby obtains the photosensitivity.

This photosensitive drum 10 is made by layers of an organic photosensitive material and a photoconductive material, such as amorphous silicon, on a conductive drum.

Next, this photosensitive drum 10 is irradiated with the information light emitted from an LED head 12 in accordance with the recording pattern to be printed through a rod lens array 12a. Thereby, an electrostatic latent image is formed on the photosensitive drum 10 in accordance with the information light.

The electrostatic latent image on the photosensitive drum 10 is developed into a toner image by a developing unit 13 using the two-element developing method using a two-element developer consisting of carrier and toner or the single-element developing method.

This toner image is then transferred to a cut sheet of PP, which is conveyed in synchronization with the toner image by a transfer roller 17 in the transfer unit 14, using a corona discharger.

The cut sheet PP that has passed through the transfer unit 14 is separated from the photosensitive drum 10 by a separation roller 18, and is then sent to a thermal roller fixing unit 19 for fixing the toner image.

On the other hand, the photosensitive drum 10 is discharged by a photo discharger 15, and then residual toner is removed by a cleaner 16 which has a cleaning blade is used. Then the operations explained above are carried out repeatedly.

As shown in Fig. 2, the LED head 12 includes an LED chip array 46 having a plurality of individual LED elements 41a, 41b, ..., 41n (for example, n = 4096) arranged in the form of rows (or zigzag) along the axial direction of the photosensitive drum 10, and a control IC 45 for controlling each LED element 41 in this LED chip array 46.

The control IC 45 is constructed by control elements 42a, ... 42n formed by tri-state buffers provided corresponding to the LED elements 41a, 41b, ..., 41n, hold circuits 43a, ... 43n and shift registers 44, and causes each LED element 41 in the LED chip array 46 to emit the light selectively.

The control elements 42a, ... 42n are connected to a common signal line so that the weighted light emission enable signals generated as described later can be input thereto.

The shift register 44 sequentially shifts the serial data transferred for each transfer clock input and has the same number of stages as the LED element 41.

The hold circuit 43 inputs the hold signal when n serial data is stored in the shift register 44, and therefore holds a value of the shift register 44 at that time.

Therefore, the control element 42 sets the power supply to the LED element 41 during the period in which the light emission enable signal is applied, depending on the value held by the holding circuit 43 to the ON or OFF state.

The gradation recording using the LED head in such a configuration as shown in Fig. 2 will then be explained below.

Fig. 3 is a diagram for explaining a structure of an embodiment of the LED printer of the present invention.

In this figure, numeral 31 denotes an image memory for storing the 8-bit gradation image data of the single page to be output for printing, 32 a gradation decoder for converting the gradation image data read from the image memory 31 into the 3-bit gradation data, 34a, 34b row buffers for storing 3-bit gradation data output from the gradation decoder 32, 33, 35 buffer switches constituted by, for example, a multiplexer. The buffer switch 33 selectively supplies the output of the gradation decoder 32 to one of the row buffers 34a and 34b, while the buffer switch 35 selects an output of the row buffer not selected by the buffer switch 33. The number 50 defines a ROM for storing the fluctuation correction data, which stores fluctuation correction data corresponding to each LED element 41.

An MPU 100 includes an X address counter (XADC) 101 provided therein and a Y address counter (YADC) 102, and reads the gradation image data by supplying the values of these XADC 101 and YADC 102, namely, the dot position address in the X and Y directions to the image memory 31 through the address register 109.

XADC 101 is caused to increment in synchronization with the oscillation clock of the reference clock oscillator 110 while counting up YADC 102 when there is a convey signal in time that XADC 101 becomes the end address of the storage position of the transverse direction of the image memory 31 (the axial direction of the photosensitive drum 10 corresponding to the main scanning direction), namely 4096 in the case where 4096 LED elements are used as described above, and the row clock (Fig. 4(a)) output from the address counter 121 which will be described later is input through the I/O interface 103.

In addition, YADC 102 outputs the convey signal when it reaches the end address of the storage position of the vertical direction of the image memory 31 (circumferential direction of the photosensitive drum 10 corresponding to the sub-scanning direction), informing that the output of the image data of exactly one page has been completed.

The MPU 100 stores image data sent from the main computer (not shown) that has already been received during this time and outputs the image of the next page.

The image data of each dot position read from the image memory 31 is applied to the buffer switch 33 after being converted into the gradation data of 3 bits by the gradation decoder 32.

The MPU 100, when starting the operation, outputs the set signal through the I/O interface 103 to set the T-type flip-flop 111, and also clears the row buffer 34 and resets each counter.

Thereby, an output of the T-type flip-flop 111 is input to the buffer switches 33 and 35 and the multiplexer 112, the buffer switch 33 is switched to input an output of the gradation decoder to the row buffer 34a, while the buffer switch 35 is switched to select an output of the row buffer 34b, and the multiplexer 112 is switched to input the write enable signal WE from the I/O interface 103 to the row buffer 34a.

Meanwhile, the address counter 120 counts up the reference clocks sent from the reference clock oscillator 110 and outputs such count value to the upper bit positions of the address register 140 through the AND gate circuit 130.

A count value of the address counter 121 for counting the clocks frequency-divided by the frequency dividers 113 and 114 from the reference clock of the reference clock oscillator 110 is set to the lower bit positions of the address register 140.

The frequency divider 113 outputs the first frequency-divided clock by dividing the frequency of the reference clock into the clock of 1/4096 period, while the frequency divider 114 outputs the second frequency-divided clock by dividing the frequency of the first frequency-divided clock into the clock of 1/5 period.

The value "4096" of the frequency divider 113 is equal to the number of LED elements 41 in the case that the reference clock coincides with the image data reading period from the image memory 31.

The period of the first frequency-divided clock is set to be equal to the period t1 of the sub-row clock indicated in Fig. 4(d), while the period of the second frequency-divided clock is set to be equal to the gradation row clock t2 indicated in Fig. 4(b). The row buffer 34 is accessed according to the content set in the address register 140.

That is, the address counter 120 counts up in synchronization with the gradation image data output from the image memory 31, giving the dot position address for writing or reading data to/in the row buffer 34, while the address counter 121 gives the gradation row selection address for selecting gradation rows 34a1 34a3 in the row buffer 34a and gradation rows 34b1 34b3 in the row buffer 34b.

Accordingly, the gradation data in the specified position of the row buffer 34a is stored according to the address to be set in the address register 140, and the gradation data of the predetermined position of the row buffer 34b is output through the buffer switch 35.

The counter 122 counts up the first frequency-divided clock pulse of the frequency divider 113 and outputs such a count value.

The decoder 150 decodes an output value of the counter 122. Namely, it outputs "0" if an output of the counter 122 is "1" or "1" if the output of the counter 122 is not "1".

Accordingly, since an output of the decoder 150 and the first frequency-divided clock from the frequency divider 113 are input, the AND gate 132 outputs the sub-series clock of the type in which the second clock (indicated by a broken line) is eliminated, as shown in Fig. 4(d).

Here, the second clock is extracted because it is required that the nominal ratio of the light emission enable signal must be large.

In addition, the AND gates 130 and 134 do not output the count output of the address counter 120 and the convey signal when an output of the decoder 150 is "0", that is, during the periods of second (indicated by the broken line) and third clocks of Fig. 4(d).

The address counter 123 counts up the sub-series clock output from the AND gate circuit 132 and outputs such a count value. An output of the address counter 123 is input to the lower bit position of the address register 141.

Meanwhile, since an output of the address counter 120 is set in the upper bit positions of the address register 141, an access to the fluctuation compensating ROM 50 is extended according to the content of the address register 141.

That is, the fluctuation compensating ROM 50 outputs a value according to the fluctuation characteristic of the light intensity of the LED element 41 in the dot position address in synchronization with an output of the gradation data corresponding to the dot position address from the row buffer 34b.

An output of this fluctuation compensating ROM 50 and an output of the row buffer 34b are applied through the AND gate circuit 131 to the shift register 44 in the LED head as the serial data.

An output of the address counter 123 is input to the decoder 151 through a delay circuit 180 which delays the sub-row clock indicated in Fig. 4(d) for the period t1.

As shown in Fig. 4(e), the decoder 151 selects the monomultivibrator (MMB) 161 when an output of the address counter 123 is "0", or the MMB 162 when an output is "1", or the MMB 163 if an output is "2", or the MMB 164 if an output is "3".

The MMB 161 outputs the light emission enable signal of the light emission period e₁, while the MMB 162 outputs the light emission enable signal of the light emission period e₂, the MMB 163 outputs the light emission enable signal of the light emission period e₃, and the MMB 164 outputs the light emission enable signal of the light emission period e₄.

Therefore, since the address counter 123 repeats the count-up operation of the count value from "0" every time the address counter 121 counts up and outputs the gradation series clock, the light emission enable signal indicated by Fig. 4(f) is input to a control element 42 of the LED head through the OR circuit 171.

In addition, the light emission period e1 has the light emission time of eight time units, while the light emission period e2 has the emission time of four time units, the light emission period e3 has the emission time of two time units, and the light emission period e4 has the emission time of one time unit. A combination of such time units provides the light emission time of 0 15 time units.

Fig. 5 indicates the content of the light quantity compensation ROM 50. As shown in Fig. 5, the light quantity compensation data is stored in the form of four bits for each LED element 41 to form the sub-series to select the light emission time. As previously explained, the light emission time of eight time units is set for sub-row 0, the light emission time of four time units for sub-row 1, the light emission time of two time units for sub-row 2, and the light emission time of one time unit for sub-row 3.

For example, the LED element providing the dot position address 0 performs light emission in the sub-row 0 and sub-row 3 and continues light emission for a total of nine time units. The LED element providing the dot position address 1 performs light emission in the sub-row 0 and sub-row 1 and continues light emission for a total of 12 time units.

Since the light intensity of the LED element is generally scattered in the constant range, it is desirable that the light emission time of the LED element having a medium light intensity is set in advance, and the light emission time of the other LED elements is set around such a light emission time.

In this embodiment, the light emission time of the LED element having a medium light intensity is set to the 12 time units, and light amount compensation is carried out within the range of the 8 15 time units.

It is self-evident that a finer light quantity compensation can be achieved by setting the larger adjustable time units is possible by increasing the number of subseries.

When a voltage is constant, the LED element increases the light quantity exactly in proportion to the duration of an applied pulse. Accordingly, it is no longer necessary to provide the light quantity value at each gradation level for each LED element of the light quantity compensating ROM 50, and it is sufficient that a common compensation value for each gradation level is stored in the memory.

Operations of this embodiment are explained with reference to Fig. 2 and Fig. 6.

The MPU 100 resets each counter through the I/O interface 103 and outputs the write enable signal WE to the multiplexer 112. It also applies the addresses specified by XADC 101 and YADC 102 to the image memory 31 in synchronization with the clock of the reference clock generator 110 and outputs the gradation image data read from the image memory 31 to the gradation decoder 32.

The gradation image data is read in synchronization with the reference clock from the reference clock oscillator 110 as shown in Fig. 6(a), and the gradation image data "0", "1", "2", ... is read for each dot position address (0), (1), ... as shown in Fig. 6(b). This gradation data is converted into the gradation data of 3 bits by the gradation decoder 32, and is then stored in the row buffer as shown in Fig. 6(c). That is, in the gradation data with the gradation level "0", three bits are all "0", and gradation data of the gradation level "1" is converted to "100", the gradation data with the gradation level "2" is converted to "110". The gradation data with the gradation level "3" is converted to the light pattern "111" in which three bits are all "1".

The gradation series light pattern does not allow the LED element to light up for gradation level 0, causes the LED element to light up for gradation level 1 during the period of gradation series 0, causes the LED element to light up for gradation level 2 during gradations 0 and 1, and causes the LED element to light up for gradation level 3 during gradations 0, 1, and 2.

That is, when the gradation level is "0", the level "0" is stored in the row buffers 34a1 34a3 (or 34bl 34b3) as shown in Fig. 6(d). In addition, when the gradation level is "1", the level "1" is stored only in the row buffer 34al (or 34b1) and the level "0" is stored in the other row buffers.

In addition, when the gradation level is "2", only the row buffers 34a1 and 34a2 (or 34bl and 34b2) are set to "1", and the remaining row buffers 34a3 (or 34b3) are set to "0". When the gradation level is "3", the row buffers 34a1 34a3 (or 34b1 34b3) are all set to "1".

Since the address counter 120 counts up in synchronization with an output of the reference clock oscillator 110, the dot position address is set in the address register 140, and a count value of the address counter 121 is "0" in this case, the first bit among the gradation data of three bits output from the gradation decoder 32 is stored in the row buffer 34a1. The other bits are sequentially stored in the storage position in the row buffer 34a1 corresponding to the dot position address indicated by the count value of the address counter 120.

In addition, the other row buffer 34b1 is selected by the switch 35, and the data of the corresponding position is output to the one input terminal of the AND gate circuit 131.

That is, as shown in Fig. 6(d), when the light pattern is assumed to be stored in the row buffer 34, since the stored content of the dot position address (0) is "0", "0" is outputted.

Here, since a value of the counter 122 is "0" and the address counter 123 outputs "0" as the sub-row address, the fluctuation compensating ROM 50 reads the value "1" which is in the storage position of the dot position address "0" with the sub-row address "0" and then applies such a value to the other input of the AND gate circuit 131. However, since the other input of the AND gate circuit 131 is "0", "0" is output as shown in Fig. 6(e).

Each time the address counter 120 counts up, the dot position address of the row buffer 34 and the dot position address of the fluctuation compensating ROM 50 are renewed, and thereby data writing and reading operations are sequentially carried out.

Since the reference clock from the reference clock oscillator 110 is input to the shift register 44 of the LED head, an output of the AND gate circuit 131 is sequentially shifted and stored in the shift register 44.

When the address counter 120 counts up 4096, the feed signal is output to the LED head as the hold signal. Therefore, the content set in the shift register 44 is then set in the hold circuit 43.

In addition, the feed signal from the address counter 120 is input to the counter 124.

An output of the counter 124 is input to the decoder 152, which outputs "1" when the count value is "0" or outputs "0" when the count value "1" is "4". Accordingly, the AND gate circuit 139 outputs the write enable signal only when the first sub-series clock shown in Fig. 4(b) is output. The address counter 120 again starts the count-up operation of the reference clock generated from the reference clock oscillator 110.

In this case, since an output of the counter 122 becomes "1", an output of the decoder 150 becomes "0", and an output of the address counter 120 is turned on by the AND gate circuit 130, the read operation for the row buffer 34a1 and the fluctuation compensating ROM 50 is not carried out.

At this time, the first sub-series clock (Fig. 4(d)) is input to the decoder 151 through the delay circuit 180. Accordingly, the decoder 151 causes MMB 161 to select the selection operation and applies the light emission enable signal of the light emission period e1 of eight time units to the control element 42.

As a result, only the LED element for which "1" is set in the hold circuit 43, that is, the LED element 41 having the gradation data other than "0", is controlled.

When the address counter 120 counts up to "4096" as the count value and the address counter starts the count-up operation of the reference clock sent from the reference clock oscillator 110 again, an output of the counter 122 becomes "2", but since the content of the address counter 121 is still "0", the read operation of the row buffer 34b1 and fluctuation compensating ROM 50 are carried out again.

At this time, an output of the counter becomes "2", and the decoder 150 outputs "1". Therefore, since the address counter 123 counts up and becomes "1", the dot position address and the sub-row address "1" is set in the address register 141.

Accordingly, the content of the sub-row address "1" is read from the fluctuation compensating ROM 50, and it is then applied to the AND gate circuit 131. Thereby, the data read from the row buffer 34b1 is logically calculated as explained above and then input to the shift register 44 of the LED head.

At this time, since the write enable signal WE from the AND gate circuit 139 is turned on, the write operation to the row buffer 34a1 is not performed.

When the address counter 120 counts up and the feed signal is output, the content of the shift register 44 is set in the latch circuit 43 as explained above. Meanwhile, the decoder 151 inputs the count value "1" of the address counter 123, and therefore, it selects MMB 162 and controls the LED element 41 by applying the light emission enable signal of the light emission period e2 of the four time units to the control element 42.

As explained above, the previously explained operations are repeated and executed sequentially to carry out the processing for the gradation series "0".

When the address counter 123 counts up, the feed signal is output to the counter 122, and it starts the count-up operation again from "0".

In this case, the gradation series clock is input as the second frequency-divided clock from the frequency divider 114 to the address counter 121. It is then counted up and the count value "1" is set in the address register 140.

Accordingly, since the row buffers 34a2 and 34b2 are selected and the counter 134 counts up, an output of the decoder 152 becomes "1". In addition, the MPU 100 again causes YADC 101 to perform the count-up operation under the condition that the count-up operation of YADC 102 stops when an output of the frequency divider 114 is provided.

Thereby, the operation for the next gradation row "1" is carried out by repeatedly executing the processings on the row buffers 34a2 and 34b2 as previously explained.

That is, as shown in Fig. 6(f), the signal of the gradation series 1 is applied to cause the LED element 41 at the dot position address "2", "3", etc. of the gradation data of "2" or higher to perform the light emitting operation. Next, the signal pattern of the gradation series "2" as shown in Fig. 6(g) is applied to the LED element 41 at the dot position address "3" with the gradation of "3" to perform the light emitting operation by repeatedly performing the above operations.

When the operations for each gradation row are completed, the address counter counts up 121, and the feed signal (series clock in Fig. 4(a)) is input to the T-type flip-flop 111. Therefore, the T-type flip-flop 111 inverts its output.

Accordingly, the buffer switch 33 inputs an output of the gradation decoder 32 into the row buffer 34b, while the buffer switch 35 selects an output of the row buffer 34a, and the multiplexer 112 is switched to apply the write enable signal to the row buffer 34b.

When this row clock (Fig. 4(a)) is output, YADC 102 of MPU 100 counts up and sets the read address in image memory 31 to read the gradation image data of the next line.

The MPU 100 operates the controllers 190 and 191 through the I/O interface 103 for each output of the first frequency-divided clock, that is, in synchronism with the output timing of the clock output from the frequency divider 113 or the timing of the counter 122 for the count-up operation, and rotates a stepping motor 195 for driving the photosensitive drum 10 and a stepping motor 196 for driving the sheet conveying rollers 32 and 33 for the one sub-row in the sub-scanning direction.

By sequentially repeating the operations explained above, the gradation recording can be realized under the condition that the fluctuation is compensated.

Fig. 7 is a diagram for explaining a structure of the further embodiment of the LED printer of the present invention.

The elements similar to those in Fig. 3 are designated by the same numbers, and explanation will not be repeated.

In Fig. 7, numerals 210 and 211 denote row buffers storing gradation image data read from the image memory 31, 220 a light amount compensation ROM storing the light amount compensation data of each LED element 41 for each gradation level, 230 an address register setting addresses for accessing the light amount compensation ROM 220, 231 an address register setting addresses for accessing the row buffers 210, 211, 232 an address counter for counting the reference clock generated by the reference clock oscillator 110, 240 a frequency divider for dividing the reference clock from the reference clock oscillator 110 into the period of 1/4096 and outputting a third frequency-divided clock (the clock in the same period as the period t3 of the sub-series clock shown in Fig. 8(b)), 250 a counter for counting the third frequency-divided clock, 260 a decoder which outputs "0" only when the count value of the counter 250 is "1", that is, when the second clock (indicated by the broken line) of Fig. 8(b) is output, 270, 271 AND gates for inputting an output of the decoder 260 to the one terminal, 251 a counter for counting an output of the AND gate circuit 270, 281 288 comparators each inputting an output of the counter 250. The comparator 281 controls the monomultivibrator (MMB) 301 which outputs the light emission enable signal of 128 time units when a count value of the counter 250 is 2, the comparator 282 controls the MMB 302 which outputs the light emission enable signal of 64 time units when a count value of the counter 250 is 2, the comparator 283 controls the MMB 303 which outputs the light emission enable signal of 32 time units when a count value of the counter 250 is 3, the comparator 284 controls the MMB 304 which outputs the light emission enable signal of 16 time units when a count value of the counter 250 is 4, the comparator 285 controls the MMB 305 which outputs the light emission enable signal of 8 time units, when a count value of the counter 250 is 5, the comparator 286 controls the MMB 306 which outputs the light emission enable signal of 4 time units, when a count value of the counter 250 is 6, the comparator 287 controls the MMB 307 which outputs the light emission enable signal of 2 time units, when a count value of the counter 250 is 7, the comparator 288 controls the MMB 308 which outputs the light emission enable signal of 1 time unit, when a count value of the counter 250 is 8, 290 is an OR circuit for outputting the OR output of MMBs 301 308 as the light emission enable signal of the LED head, 252 is a counter for counting the feed signal from the address counter 232, 253 is a decoder, which outputs "1" if the count value is "0" or "0" if the count value "1" is "7".

Fig. 9 is a diagram showing the contents of the light quantity compensation ROM in the conversion table. The light quantity compensation ROM 220 stores the Sub-row light pattern of each LED element for each gradation level.

The light emission time is set according to the light intensity of the LED element based on the light amount compensation data, for example, 80 time units for gradation level 1, 160 time units for gradation level 2 and 240 time units for gradation level 3.

In the above-described structure, the MPU 10 reads the gradation image data from the image memory 31 as in the case of the embodiment of Fig. 3.

In this case, the MPU 100 sets the T-type flip-flop 111 so that the buffer switch 33 selects the buffer memory 210, and therefore the gradation image data is stored in the buffer memory 210.

On the other hand, the address counter 232 counts up in synchronization with the reading operation of the gradation image data from the image memory 31. Therefore, the write/read addresses of the row buffers 210, 211 are set for each gradation image value in the address register 231.

Accordingly, the gradation image data from the image memory 31 is sequentially stored at the dot position address 0 of the row buffer 210. In addition, the gradation image data is sequentially read from the dot position address 0 of the row buffer 211. The read gradation image data is switched to the intermediate bit position of the address register 230.

Since a count value of the address counter 232 is set in the upper bit position of the address register 230, while an output (count value "0" at this time) of the counter 251 is set in the lower bit position of the address register 230, as is clear from Fig. 9, the value "0" stored in the storage position where the dot position address is 0 (corresponding to the LED element 41a) and the sub-row is "0" with the gradation level (for example, "1") indicated by the gradation image data is read from the light amount compensation ROM 220 and then output to the shift register 44 of the LED head.

The dot position addresses set in the address register 231 and the address register 230 are sequentially renewed for each count-up of the address counter 232, and the data for each LED element 41 is read.

That is, in the case where the gradation level indicated by the gradation image data corresponding to the dot position address 1 is "2", as is clear from Fig. 9, the value "1" stored in the storage position corresponding to the sub-row "0" is read from the light amount compensation ROM 220 and then output to the shift register 44.

When the address counter 232 has counted up to 4096, the feed signal is sent to the holding circuit 43 as the hold signal, it is then sequentially shifted to the shift register 44, and the set data is set in the hold circuit 43.

At this time, a count value of the counter 240 is input to the comparators 281, 288 through the delay circuit 291. Here, since a count value of the counter 250 is "1", only the comparator 281 obtains a comparison output, and only the MMB 301 is selectively controlled and outputs the light emission enable signal of 128 time units.

The address counter 232 outputs the feed signal, a count value of the counter 250 becomes "1", an output of the decoder 260 becomes "0" and is input to the AND gate circuits 270 and 271. Therefore, the outputs of the address counter 232 and the frequency divider 240 are not input to the address registers 231, 230 and counter 251, the access for the row buffers 210, 211 and the light quantity compensation ROM 220 is not performed, and the count-up operation of the counter 251 is not performed.

In addition, the comparators 281 288 do not receive the comparison output, the MMBs 302 308 do not operate, and the MMB 301 continues the output operation of the light emission enable signal of 128 units of time.

Since the count value of the counter 250 becomes "2" when the address counter 232 outputs the next feed signal, an output of the decoder 260 returns to "1", outputs of the address counter 232 and the frequency divider 240 are converted into the address registers 230, 231 and the counter 251 are input, access is made to the row buffers 210, 211 and the light amount compensation ROM 220 as previously explained, and the count-up operation of the counter 251 is also carried out.

As described above, the gradation recording of the one line is carried out by sequentially reading the data from the light amount compensation ROM 220 and then setting it into the shift register 44.

When the counter 251 counts up the value "7" and outputs the feed signal, the counter 240 is reset and is then input to the T-type flip-flop 111, which switches the buffer switches 33, 35 and the multiplexer 112.

The MPU 100 causes the XADC 101 and the YADC 102 to count up and set the count value in the address register to read the gradation image data of the next line, and also causes the row buffer 211 through the buffer circuit 33 to store the gradation image data of the next line by reading it from the image memory 31.

By continuing the operations described above, the gradation recording operation of the next line can be performed, and the gradation recording operation of a single page can be performed.

As explained above, in this version the gradation series clock is different from the first version not provided, and the light amount compensation and gradation recording of each LED can be carried out by combining the light sub-rows.

In the above embodiments, the LED elements were used as the individual light emitting elements, but the present invention is not limited thereto. That is, other individual light emitting elements may be used, and a liquid crystal shutter in which a plurality of common light sources are arranged like a row may be used.

In addition, the present invention can also be applied to the optical system for exposing the electrophotographic printer which realizes color recording.

Furthermore, in each embodiment explained above, the monomultivibrator was used for outputting the light emission enable signal of the different duration, but the present invention is not limited thereto.

For example, since the duration for performing one access to the memory by the MPU is already known, the periodic memory access is performed by the MPU. The number of accesses to the memory, which is different for each sub-row clock, is synchronized with the sub-row clock for the count-up operation, and the light emission enable signal is output during the period until the count value reaches the predetermined value.

Industrial applicability

According to the present invention, since a fluctuation in the light intensity of a single light-emitting element is compensated using the weighted pattern when gradation recording is carried out using individual light-emitting elements, high-quality gradation recording can be realized with a smaller storage capacity.

Claims (6)

1. Electrophotographic printer, with a linear arrangement of a plurality of individual recording elements (41a to 41n), Means (34a, 34b; 210, 211, 220) for holding gradation information concerning the individual recording elements (41a to 41n) of the plurality, Means (50; 220) for holding correction information for correcting variations in the light intensity characteristics between the individual recording elements (41a to 41n) of the plurality, and Control means (42a to 42n) for controlling the individual recording elements (41a to 41n) of the plurality to emit light for time periods depending on the gradation information and the correction information, marked by Enable means (161, 162, 162, 164, 171; 301 to 308, 291) for providing said control means (42a to 42n) with successive enable signals of different respective durations (e₁, e₂, e₃, e₄; (128), (64), (32), (16), (8), (4), (2), (1)), which control means are enabled to control said individual recording elements (41a to 41n) to emit light only for enabled periods of the duration of said successive enable signals, thereby enabling light emissions from said individual recording elements in different enable periods be weighted differently according to the duration of those periods, Selection means (43, 44) operable to select, for each individual recording element (41a to 41n) of the plurality and for each of the successive enabling periods of the control means (42a to 42n), whether the respective recording element is to be controlled to emit light in the respective enabling period in dependence on the gradation information and the correction information. 2. Printer according to claim 1, characterized in that the selection means include, a shift register (44) having storage stages in the same number as the recording elements (41a to 41n) of the plurality, hold circuits (43) corresponding respectively to the storage stages of the shift register (44) and for storing the values stored in those storage stages in response to the application of a hold signal to the hold circuits, and the control means (42) include control elements (42a to 42n) each connected to outputs of respective holding circuits (43) operable to selectively control respective recording elements (41a to 41n) according to the values stored in the respective holding circuits (43), whereby (a) the storage stages of the shift register (44) are loaded with selection data indicating whether respective recording elements (41a to 41n) corresponding to the stages are to be controlled to emit light in a next enable period of the control means (42), (b) a hold signal is applied to the hold circuits (43) to store the selection data in the hold circuits, and (c) the enable signal (e₁, e₂, e₃, e₄; (128), (64), (32), (16), (8), (4), (2), (1)) is applied to the control devices (42) for this next enable period, and (a) to (c) are repeated for each subsequent enabling period of the control devices (42). 3. Printer according to claim 1 or 2, characterized in that the enable signals, and thus the enable periods, have respective durations (e₁, e₂, e₃, e₄; (128), (64) (32), (16), (8), (4), (2), (1)) which are different multiples of a unit or minimum duration, which multiples are, for example, powers of two, whereby light emissions from the individual recording elements in different enable periods are weighted according to these multiples. 4. A printer according to claim 3, characterized in that the means (50; 220) for holding correction information stores that information in a form which indicates which light emission weights are required for correction. 5. A printer according to claim 4, characterized in that the means (210, 211, 220) for holding gradation information holds that information in a form indicating which light emission weights are required for the gradation. 6. Printer according to one of the preceding claims, characterized in that the individual recording elements (41a to 41n) of the plurality are LED elements.