DE69029577T2 - Signal conversion circuit - Google Patents

Description

The present invention relates to a signal conversion circuit for converting a parallel signal into a serial signal in which the continuation of identical bits (zeros or ones) is suppressed, which (circuit) can be used, for example, in a video signal transmitter or transmitter.

In non-return-to-zero coding (NRZ) and alternating mark inversion (AMI) coding, which are often used as a transmission coding method, there is a possibility that zeros or ones may persist for a long period of time, which may cause synchronization problems. For this reason, various measures have been taken to prevent the persistence of zeros or ones. For example, in baseband transmission, a code for suppressing the persistence of identical bits is used. Systems using this suppression code include various systems such as a system in which NRZ data is converted into a CMI (coded mark inversion) code. Among others, there is a system in which (n+1)-bit parallel data is converted into serial data and a complementary code is inserted into a redundant bit for data transmission.

The system includes a farallel input/serial output type shift register with as many input terminals as bits are present in the parallel data (5 bits in this example). When the parallel data is received, the shift register is supplied with a load signal LOAD and a shift clock signal CLKS from a timing generator. The parallel data is loaded into the shift register synchronously with the load signal LOAD and then read out serially from the shift register as serial data SDL synchronously with the shift clock signal CLKS. The shift clock signal CLKS is shaped so that clock pulses are removed or extracted from a clock signal CLK1 at a frequency corresponding to six times the transfer rate or flow (rate) of the parallel data, one pulse every sixth pulse. The serial data SD1 read out from the shift register thus has a redundant bit added to the serial data obtained by serial conversion of the parallel data.

The serial data SD1 with (each) one redundant bit is therefore read out from the shift register. The data SD1 is input into a complementary code insertion circuit, where, after reversing its sign, it is subjected to logical processing in synchronism with an insertion time clock signal CLOAD, so that a complementary code is inserted into the redundant bit. The serial data with inserted complementary code is output from the insertion circuit in synchronism with the clock signal CLK1.

In this way, serial data SD is obtained by converting 5-bit parallel data into 6-bit data with a complementary code. The transmission of such data SD suppresses the continuation of eg zeros in parallel data to a maximum of 5 bits, so that the data can be reproduced more reliably in a relay station or a receiver.

However, the signal conversion circuit described above requires a shift register for parallel/serial conversion and a complementary code insertion circuit because it is designed to convert parallel data into serial data having a redundant bit and insert a complementary code into the redundant bit. In addition, the timing clock generation circuit is also required to generate an insertion timing clock signal and a special shift clock signal CLKS and a load signal LOAD. For this reason, the conventional signal conversion circuit requires a complex and expensive circuit structure.

Prior art publication US-A-4 502 143 discloses a system for suppressing consecutive identical digits, wherein a single bit is inserted for each predetermined number of input digits and this insertion bit is a complement of a digit of preceding k-bits. In other words, this known system comprises means for inserting an additional complementary bit of preceding k-bits for each m input bits.

Furthermore, the prior publication "Patent Abstracts of Japan", Vol. 9, No. 106, May 1985, page 1829, discloses a parallel data transmission method in which a parallel data input is subjected to scrambling with a pseudo-random series which produces an output signal a pseudo random generator circuit at an exclusive OR gate and converted into a random code. This method involves a technique for suppressing the generation of consecutive zeros by adding a 1-bit to an input signal and using this bit as a complementary code and a field synchronism bit of a preceding bit. Digital data is subjected to speed conversion by a speed converter having input and output ring counters and a memory, and a complementary code of given 1-bit data of input data is inserted at a predetermined timing at which the speed converter detects a phase difference.

An object of the present invention is to provide a signal conversion circuit which is simply constructed and has a low circuit complexity.

This object is achieved according to this invention with a signal conversion circuit specified in claim 1.

The signal conversion circuit includes a complementary code insertion circuit for converting first (n+k)-bit data (where n and k are integers) containing n-bit original data into second data and inserting a complementary code into the additional k bit(s), and a scramble circuit for generating a pseudo-random code for obtaining the complementary code in the output data from the complementary code insertion circuit and scrambling the output data. by the complementary code insertion circuit according to the pseudo-random code.

In this signal conversion circuit, transmission data is transmitted with the complementary code rule maintained so that the position of the complementary code can be easily and surely detected at a relay station or a receiver. Consequently, a predetermined process such as a descrambling process can be performed on the transmission data. In addition, since the scrambling process can be performed after the insertion of the complementary code, there is no need to perform an operation of adding additional bits and an operation of individually inserting a complementary code into the additional bits by means of separate circuits, so that the signal conversion circuit can have a simple circuit construction.

A better understanding of this invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

Fig. 1 is a block diagram of a signal conversion circuit which does not embody this invention, but is useful for its understanding,

Fig. 2 is a timing diagram to explain the operation of the circuit according to Fig. 1,

Fig. 3 is a block diagram of a signal conversion circuit according to an embodiment of this invention,

Fig. 4 and 5 block diagrams of main parts of the circuit of Fig. 3,

Fig. 6 and 7 Timing diagrams to explain the operation of the circuits according to Fig. 4 and 5 and

Fig. 8 is a block diagram of a scrambler in a signal conversion circuit according to another embodiment of this invention.

A signal conversion circuit is described below with reference to Fig. 1. For this signal conversion circuit, the description applies to a case in which 6-bit parallel data including 5-bit parallel input data D0-D4 and one-bit data D5 is converted into serial data.

The signal conversion circuit includes a parallel input/serial output type shift register 10 having input terminals P0 - P5 which are one (1) larger than the number of bits in the parallel data D0 - D4, a timing circuit 20, and an inverter. The timing circuit 20 includes a D flip-flop 21 connected to receive or take out clock signals CLK0 and CLK1, and a NOR gate 22 connected to receive an output signal Q of the flip-flop 21 and a clock signal CLK0.

In the signal conversion circuit, the D flip-flop 21 latches a clock signal CLK0 having a period corresponding to the data flow of the parallel data D0 - D4 in synchronism with the clock signal CLK1 having a frequency corresponding to the data flow of serial data SD, which is six times the data flow of the parallel data. The output signal Q of the flip-flop 21 is NORed with the clock signal CLK0 in the NOR gate 22 to output a load signal LOAD, which in turn is supplied to a load terminal LD of the shift register 10.

The inverter 30 is provided for inverting the bit D0 of the parallel data D0 - D4; the inverted bit D0 is supplied to the input terminal PO of the shift register 10. To shift the clock input terminal CK of the shift register, the clock signal CLK1 is applied as it is.

In operation, parallel data P0 - P4 are applied as they are (unchanged) to the input terminals P1 - P4 of the shift register 10, while the bit D0 of the parallel data is inverted by the inverter 30 and then applied as a complementary code to the input terminal PO of the shift register 10. In this state, when a load signal LOAD is generated by the timing circuit 20 in synchronism with the timing of arrival of the parallel data P0 - P4 as indicated in Fig. 2, the parallel data and the complementary code are loaded into the shift register 10 in synchronism with the load signal LOAD. The parallel data and the complementary code are serially output in the order of DO, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D22, D33, D44, D55, D66, D77, D88, D90, D110, D120, D130, D140, D150, D160, D170, D180, D190, D210, D220, D230, D240, D310, D320, D330, D440, D550, D660, D670, D790, D810, D920, D930, D940, D110, D120, D130, D140, D150, D160, D171, D182, D192, D210, D320, D330, D440, D550, D660, D670, D810, D920, D110, D120, D130, D140, D150, D210, D330, D340, D440, D550, D660, D670,

D2, D3 and D4 are read, thereby providing serial data SD. This means that parallel/serial converted data SD with inserted complementary code is output from the shift register.

The above signal conversion circuit avoids the need for providing a separate circuit for inserting a complementary code, so that the signal conversion circuit can have a simple circuit structure and a small size. In addition, the timing circuit 20 only needs to generate a load signal LOAD, thereby enabling the significant simplification of its circuit arrangement. As a result, the entire circuit structure of the signal conversion circuit also becomes simple and small. In addition, this signal conversion circuit also enables the conversion of 4-bit parallel data D0 - D3 into serial data by means of the input terminals P0 - P4 of the shift register 10 without any circuit modification if only the ratio between the clock signals CLK0 and the clock signal CLK1 is changed.

In the above embodiment, the parallel data consists of five bits. Even if the parallel data consists of three bits, four bits or more than five bits, the present signal conversion circuit can be realized using a shift register having input terminals equal in number to the number of bits in the parallel data plus one (1). Although the above signal conversion circuit uses a shift register in which the number of input terminals is equal to the number of bits in the parallel data D0 - D4 plus one (1), a shift register in which the number of input terminals is equal to a maximum

number of bits of parallel data plus one (1) to convert parallel data having bits smaller than its maximum number of bits into serial data. For example, in the case of converting a video signal into a digital signal for transmission, where bits are sufficient for the number of bits in parallel data, a shift register having input terminals of a number corresponding to 10+1 bits is provided in advance; in another case, this shift register can be used to convert parallel data of, for example, 8 bits into serial data. In these two cases, the signal conversion circuit can be used without any circuit modification. Accordingly, a signal conversion circuit of a wider application range and increased versatility can be provided. In addition, the signal conversion circuit is easy to integrate and its size is reduced. The number of bits of the complementary code, the position in which the complementary code is inserted, and the timing or point of loading the parallel data D0 - D4 can be varied in various ways.

An embodiment of this invention is described below with reference to Fig. 3.

A signal conversion circuit according to this embodiment is provided with a scrambling capability in addition to the features of the previous signal conversion circuit and comprises a complementary code insertion circuit 101 and a scramble circuit 102.

Assuming that incoming original parallel data has bits D0 - D4, the complementary code insertion circuit 101 comprises a parallel input/serial output type shift register 111 having input terminals P0 - PS, the number of which corresponds to 6 bits and is one (1) larger than the number of bits in the parallel data D0 - D4, a timing circuit 112 and an inverter 113. The timing circuit 112 consists of a D flip-flop 114 connected to receive clock signals CLK0 and CLK1, and a NOR gate 115 connected to receive the output signal of the flip-flop 114 and the clock signal CLK0. The clock signal CLK0 defining the transfer rate of the parallel data D0 - D4 is latched by the D flip-flop 114 in synchronism with the clock signal CLK1 defining the transfer rate (six times the parallel data) of the serial data SD. The output signal Q of the flip-flop 114 is NORed with the clock signal CLKO in the NOR gate 115 so that a load signal LOAD is supplied therefrom to a load terminal LOAD of the shift register 111. The inverter 113 serves to invert the bit D4 of the parallel data D0 - D4 for supplying the inverted bit D4 to the shift register input terminal P5 which is located on the most significant bit side or MSB side. The clock signal CLK1 is supplied as it is to the shift clock input terminal CK of the shift register 111.

On the other hand, the scramble circuit 102 comprises an M-series generator 121 for generating a pseudo-random pulse train MP, a control circuit 122 for controlling the operation of the M-series generator 121, and an exclusive OR gate 123 for exclusive ORing the serial data SD output from the complementary code insertion circuit 101 and the pseudo-random pulse train MP generated by the M-series generator 121 to Scrambling the serial data SD. The control circuit 122 consists of, for example, a D flip-flop 124 and an AND gate 125 (see Fig. 5). The load signal LOAD generated by the timing circuit 112 of the complementary code insertion circuit 101 is delayed by one bit time and inverted by the D flip-flop 124. The AND gate 25 is enabled or switched by the signal LOAD' delayed by one bit time and inverted to provide a control clock signal CS.

In such a signal conversion circuit, the incoming parallel data is applied as it is to the input terminals P0 - P4 of the shift register 111; the bit D4 of the parallel data is inverted by the inverter 113 and applied as a complementary code to the input terminal P5 of the shift register 111. The parallel data D0 - D4 and the complementary code are loaded into the shift register 111 in synchronism with the load signal LOAD generated by the timing circuit 112 in synchronism with the timing or point of arrival of the parallel data (see Fig. 6). The parallel data and the complementary code are read out from the shift register 111 serially in the order of D0, D1, D2, D3, D4 and to be output as serial data SD. The shift register 111 outputs serial data SD in which a redundant bit has been added by the serial/parallel conversion and a complementary code has been inserted into the redundant bit.

In the scramble circuit 102, on the other hand, the control clock signal C5 is generated based on the load signal LOAD and the clock CLK1 supplied by the timing circuit 112 of the complementary insertion circuit 101. According to Fig. 7, the control clock CS is a pulse train in which a pulse corresponding to the complementary code in the serial data SD is removed or eliminated. For this reason, a pseudo random pulse train MP in which code change is prohibited at positions corresponding to the complementary code law generation positions (D4, ) of the serial data SD as shown in Fig. 7 is generated by the M series generator 121 in synchronism with the clock control signal CS. Assuming that such serial data SD as shown in Fig. 7 is output from the complementary code inserting circuit 101 and a pseudo random pulse train MP as shown in Fig. 7 is supplied from the M series generator 121, a signal SSD shown in Fig. 7 is output from the exclusive OR gate 123. This means that serial data SSD is output in which bits D0 - D4 are scrambled by the pseudo random pulse series MP, and the complementary code rule in the serial data SD is maintained.

Therefore, when transmitting such serial data SSD, the complementary code can be easily and reliably detected by a relay station or a receiver from the transmission data because the complementary code rule between D4 and N is maintained, so that the signal processing such as error checking and phase adjustment as well as the descrambling process can be easily and reliably carried out. In addition, since a scrambling process can be carried out on data into which a complementary code has been inserted, the conversion of parallel data D0 - D4 into serial data SD, namely the addition of a redundant bit by flow conversion, and the insertion of the complementary code into the redundant bit can be carried out together. by the shift register 111. As a result, the signal conversion circuit can be designed simply and with little circuit complexity.

In the described embodiment, the scramble circuit uses the M-series generator 121. Alternatively, it may use a self-synchronizing scramble circuit which performs the scrambling process by self-synchronization instead of using the M-series generator 121 and the exclusive OR gate 123. Fig. 8 shows an example of a self-synchronizing scramble circuit; this consists of five-stage shift registers 131 - 135 and exclusive OR gates 136 and 137. In this circuit, the output signal SD of the complementary code insertion circuit 101 is input to the first-stage shift register 131 via the exclusive OR gate 137. Outputs of the second-stage shift register 132 and the last-stage shift register 135 are connected to the exclusive OR gate 136.

An output signal of the exclusive OR gate 136 and the signal SD are subjected to an exclusive OR operation in the exclusive OR gate 137.

In the embodiment described, the control clock CS is generated in the control circuit 122 using the load signal LOAD generated by the timing circuit 112 of the complementary code insertion circuit 112 and the clock signal CLK1. Alternatively, the position or location at which the complementary code D4 is to be inserted may be detected from the serial data SD to generate a control clock signal CS based on the detection. Furthermore, as in the previous embodiment, a shift register having a number of input terminals corresponding to a maximum p of the largest number of bits of parallel data plus one (1) may be provided in advance (by default) to convert parallel data whose bit number is smaller than the maximum number of bits. Namely, when a video signal is converted into a digital signal for transmission, 10 bits are sufficient for the number of bits of parallel data. In this case, therefore, a shift register having a number of input terminals corresponding to 10+1 bits may be provided in advance to convert parallel data into serial data in other applications. For example, in the case of 8-bit parallel data, the inverted output of the eighth bit may be applied to the ninth input of the shift register. In addition, the embodiment may be modified such that the inverter 113 is arranged on the LSB side as shown in Fig. 1. In this case, the scramble process can be carried out while maintaining the complementary code rule and without any circuit modification of the conversion circuit. This enables a wide range of applications and increased versatility of the signal conversion circuit. In addition, the integrated circuit version of the circuit becomes simple so that its circuit scale can be smaller. The configuration of the complementary code insertion circuit, the configuration of the scramble circuit, the number of bits of the input data, the number of bits of the complementary code, the position at which the complementary code is to be inserted, and the timing of loading the parallel data into the shift register can be variously modified without departing from the scope of the present invention.

As described in detail above, according to the present invention, a signal conversion circuit -

which has a simple circuit structure and can obtain transmission data in which a complementary code rule is surely preserved by generating a pseudo-random code for preserving the complementary code rule in data output from the complementary code insertion circuit and performing a scramble process on the data output from the complementary code insertion circuit in accordance with the pseudo-random code.

Claims (3)

1. Signal conversion circuit with: a parallel input/serial output type shift register (111) supplied with an input signal having a first number (n) of bits for converting a parallel signal into a serial signal, the parallel signal including the input signal and being formed of a second number (n + k) of bits which are at least one (k) bit more than the first number (n) of bits, an inverter (113) for inverting at least one bit of the input signal and for adding an inverted bit signal to the input signal to contain complementary bits in the serial data, and a scrambler device (102) for scrambling the serial signal from the shift register (111) according to a pseudo-random code of the serial data, characterized in that the scrambler device (102) comprises: an M-series generator (121) for generating a pseudo-random pulse sequence (MP), a control circuit (122) for controlling the operation of the M-series generator (121) such that a clock pulse from the pseudo-random pulse sequence for each of the complementary bits ( ) is suppressed, and a gate circuit (123) for scrambling the serial signal (SD) from the shift register (111) with the pseudo-random pulse train (MP) from the M-sequence generator (121). 2. Signal conversion circuit according to claim 1, characterized in that the control circuit (122) comprises a flip-flop (124) for delaying a load signal (LOAD) synchronous with the incoming timing of the input signal by one bit time and for inverting it and an AND gate (125) responsive to the inverted signal from the flip-flop (124) to provide a control clock to the M-series generator (121). 3. A signal conversion circuit according to claim 1, characterized in that the gate circuit (123) is an explosive OR circuit (123) for exclusively ORing the serial signal (SD) from the shift register (111) and the pseudo-random pulse train (MP) to output serial data (SSD).