DE69029065D1 - Logical circuitry and method for reordering for a graphic video display memory - Google Patents

Logical circuitry and method for reordering for a graphic video display memory

Info

Publication number
DE69029065D1
DE69029065D1 DE69029065T DE69029065T DE69029065D1 DE 69029065 D1 DE69029065 D1 DE 69029065D1 DE 69029065 T DE69029065 T DE 69029065T DE 69029065 T DE69029065 T DE 69029065T DE 69029065 D1 DE69029065 D1 DE 69029065D1
Authority
DE
Germany
Prior art keywords
reordering
video display
display memory
logical circuitry
graphic video
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69029065T
Other languages
German (de)
Other versions
DE69029065T2 (en
Inventor
Karl M Guttag
Ian J Sherlock
Richard D Simpson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/387,568 external-priority patent/US5233690A/en
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE69029065D1 publication Critical patent/DE69029065D1/en
Publication of DE69029065T2 publication Critical patent/DE69029065T2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Input (AREA)
  • Controls And Circuits For Display Device (AREA)
DE1990629065 1989-07-28 1990-07-27 Logical circuitry and method for reordering for a graphic video display memory Expired - Fee Related DE69029065T2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38756789A 1989-07-28 1989-07-28
US07/387,568 US5233690A (en) 1989-07-28 1989-07-28 Video graphics display memory swizzle logic and expansion circuit and method

Publications (2)

Publication Number Publication Date
DE69029065D1 true DE69029065D1 (en) 1996-12-12
DE69029065T2 DE69029065T2 (en) 1997-03-06

Family

ID=27011933

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1990629065 Expired - Fee Related DE69029065T2 (en) 1989-07-28 1990-07-27 Logical circuitry and method for reordering for a graphic video display memory

Country Status (3)

Country Link
EP (1) EP0410777B1 (en)
JP (1) JP3085693B2 (en)
DE (1) DE69029065T2 (en)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2067418C (en) * 1991-07-22 1998-05-19 Sung M. Choi Frame buffer organization and control for real-time image decompression
JPH0656546B2 (en) * 1991-07-22 1994-07-27 インターナショナル・ビジネス・マシーンズ・コーポレイション Image buffer
JP2561810B2 (en) * 1994-01-03 1996-12-11 インターナショナル・ビジネス・マシーンズ・コーポレイション Hardware-assisted pixel reformatting during bit boundary block transfers
US6643765B1 (en) 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
US7203310B2 (en) * 2001-12-04 2007-04-10 Microsoft Corporation Methods and systems for cryptographically protecting secure content
US9035168B2 (en) 2011-12-21 2015-05-19 Sunpower Corporation Support for solar energy collectors
WO2013100783A1 (en) 2011-12-29 2013-07-04 Intel Corporation Method and system for control signalling in a data path module
US10331583B2 (en) 2013-09-26 2019-06-25 Intel Corporation Executing distributed memory operations using processing elements connected by distributed channels
US11086816B2 (en) 2017-09-28 2021-08-10 Intel Corporation Processors, methods, and systems for debugging a configurable spatial accelerator
US11307873B2 (en) 2018-04-03 2022-04-19 Intel Corporation Apparatus, methods, and systems for unstructured data flow in a configurable spatial accelerator with predicate propagation and merging
US11200186B2 (en) 2018-06-30 2021-12-14 Intel Corporation Apparatuses, methods, and systems for operations in a configurable spatial accelerator
US10853073B2 (en) 2018-06-30 2020-12-01 Intel Corporation Apparatuses, methods, and systems for conditional operations in a configurable spatial accelerator
US10891240B2 (en) 2018-06-30 2021-01-12 Intel Corporation Apparatus, methods, and systems for low latency communication in a configurable spatial accelerator
US10817291B2 (en) 2019-03-30 2020-10-27 Intel Corporation Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator
US10915471B2 (en) 2019-03-30 2021-02-09 Intel Corporation Apparatuses, methods, and systems for memory interface circuit allocation in a configurable spatial accelerator
US11037050B2 (en) 2019-06-29 2021-06-15 Intel Corporation Apparatuses, methods, and systems for memory interface circuit arbitration in a configurable spatial accelerator

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4408200A (en) * 1981-08-12 1983-10-04 International Business Machines Corporation Apparatus and method for reading and writing text characters in a graphics display
JPS63104186A (en) * 1986-10-22 1988-05-09 Matsushita Electric Ind Co Ltd Picture enlarging device
US4823286A (en) * 1987-02-12 1989-04-18 International Business Machines Corporation Pixel data path for high performance raster displays with all-point-addressable frame buffers
US4882683B1 (en) * 1987-03-16 1995-11-07 Fairchild Semiconductor Cellular addrssing permutation bit map raster graphics architecture
US4807189A (en) * 1987-08-05 1989-02-21 Texas Instruments Incorporated Read/write memory having a multiple column select mode

Also Published As

Publication number Publication date
EP0410777B1 (en) 1996-11-06
DE69029065T2 (en) 1997-03-06
JPH03156576A (en) 1991-07-04
EP0410777A3 (en) 1992-10-28
EP0410777A2 (en) 1991-01-30
JP3085693B2 (en) 2000-09-11

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee