JPS63104186A - Picture enlarging device - Google Patents

Picture enlarging device

Info

Publication number
JPS63104186A
JPS63104186A JP61251124A JP25112486A JPS63104186A JP S63104186 A JPS63104186 A JP S63104186A JP 61251124 A JP61251124 A JP 61251124A JP 25112486 A JP25112486 A JP 25112486A JP S63104186 A JPS63104186 A JP S63104186A
Authority
JP
Japan
Prior art keywords
line
memory
address
data
buffer memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61251124A
Other languages
Japanese (ja)
Inventor
Takuji Katsura
卓史 桂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP61251124A priority Critical patent/JPS63104186A/en
Publication of JPS63104186A publication Critical patent/JPS63104186A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T3/00Geometric image transformations in the plane of the image
    • G06T3/40Scaling of whole images or parts thereof, e.g. expanding or contracting
    • G06T3/4007Scaling of whole images or parts thereof, e.g. expanding or contracting based on interpolation, e.g. bilinear interpolation

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To enlarge a picture which is approximate to an original picture by permitting a space product sum calculating circuit to interpolate data. CONSTITUTION:Multigradation picture data (x-lines X y-lines) is stored. Before data is transferred to a buffer memory 3 from an accessible frame memory 1 on a line basis, a CPU 7 creates an address conversion table in a look-up table LUT 5. Afterwards an address counter 4 is incremented or decremented. An address is given to the buffer memory 3 through a selector 8 and data is written in the buffer memory 3. Then an input from the selector 8 is switched to the LUT 5 from the address counter 4, which is incremented or decremented. An address is given to the buffer memory 3 through the LUT 5 and the selector 8. The space product sum calculating circuit 6 interpolates data outputted from the buffer memory 3. Picture data is written in the frame memory 1 or a display memory 2, and a picture is displayed on a display device 9.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は多値画像を拡大する画像拡大装置に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an image enlarging device for enlarging a multivalued image.

従来の技術 従来の画像拡大装置では、n倍の拡大の場合、画素をn
個続けることによシ補間処理をしないで拡大処理を実現
していた。
2. Description of the Related Art In conventional image enlargement devices, when enlarging by n times, pixels are
By continuing the process, enlargement processing was realized without interpolation processing.

発明が解決しようとする問題点 このような従来の装置では、補間処理をしていないので
モザイク画のようになるという欠点があった。本発明は
上記問題点に鑑み、画像の拡大とともに画像データの補
間を行なうことのできる画像拡大装置を提供することを
目的とする。
Problems to be Solved by the Invention These conventional devices have the drawback of not performing interpolation processing, resulting in a mosaic-like image. SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide an image enlarging device capable of enlarging an image and interpolating image data.

問題点を解決するための手段 本発明は上記目的を達成するため、フレームメモリにラ
イン単位のアクセス機能を一持たせ、画像の縦方向の拡
大を行ない、アドレスカウンタ、ルックアップテーブル
、バッファメモリによる横方向の拡大を行なう。さらに
、空間積和演算回路で補間処理を行なう。
Means for Solving the Problems In order to achieve the above object, the present invention provides the frame memory with a line-by-line access function, enlarges the image in the vertical direction, and uses an address counter, lookup table, and buffer memory. Perform horizontal expansion. Furthermore, interpolation processing is performed in a spatial product-sum calculation circuit.

作  用 本発明は上記した構成で、フレームメモリ、アドレスカ
ウンタ、ルックアップテーブル、バッファメモリにより
、拡大率に従った画像データの多重読出を行ない、空間
積和演算回路で補間処理をすることにより、画像の拡大
を行なう。
Operation The present invention has the above-described configuration, and performs multiple reading of image data according to the enlargement ratio using the frame memory, address counter, lookup table, and buffer memory, and performs interpolation processing using the spatial product-sum calculation circuit. Enlarge the image.

実施例 第1図は本発明の画像拡大装置の一実施例を示すブロッ
ク図である。第1図において、多階調画像データ(Xラ
イン×yライン)を記憶し、ライン単位にアクセスでき
るフレームメモリ1からバッファメモリ3にデータを転
送する前K CP U Tからルックアップテーブル(
以下LUTという)6にアドレス変換テーブルを作る。
Embodiment FIG. 1 is a block diagram showing an embodiment of the image enlarging apparatus of the present invention. In FIG. 1, before data is transferred from a frame memory 1 that stores multi-gradation image data (X lines x y lines) and can be accessed line by line to a buffer memory 3, a lookup table (
An address translation table is created in 6 (hereinafter referred to as LUT).

その後、アドレスカウンタ4をカウントアツプ(ダウン
)し、セレクタ8を介し、バックアメモリ3にアドレス
を与え、バックアメモリ3にデータを書込む。次にセレ
クタ8の入力をアドレスカウンタ4からLUTsに切り
換え、アドレスカウンタ4をカウントアツプ(ダウン)
L、LUT6.セレクタ8を介し、パック7メモリ3に
アドレスを与え、バッファメモリ3からの出力データを
空間積和演算回路6で補間し、フレームメモリ1.ある
いは表示メモリ2に画像データを書込、表示装置9に画
像を表示する。
Thereafter, the address counter 4 is counted up (down), an address is given to the backup memory 3 via the selector 8, and data is written in the backup memory 3. Next, the input of selector 8 is switched from address counter 4 to LUTs, and address counter 4 is counted up (down).
L, LUT6. An address is given to the pack 7 memory 3 via the selector 8, the output data from the buffer memory 3 is interpolated by the spatial product-sum operation circuit 6, and the frame memory 1. Alternatively, image data is written in the display memory 2 and the image is displayed on the display device 9.

第2図に空間積和演算回路の一実施例を示す。FIG. 2 shows an embodiment of the spatial product-sum calculation circuit.

第2図において、入力ラッチ10を介し、n個の入力ラ
インバッファ11にnラインの画像データを書込、乗算
器12で画素単位で画像データと演算子バッファ16の
演算子の乗算を行ない、加算部13で加算し、ルックア
ップテーブル14で、入力データに対して平均の値を出
力し、出力ラッチ16を介して画像データをフレームメ
モリ1゜あるいは表示メモリ2に画像データを書込、表
示装置9に表示する。
In FIG. 2, n lines of image data are written into n input line buffers 11 via an input latch 10, and a multiplier 12 multiplies the image data by an operator in an operator buffer 16 pixel by pixel. The adder 13 adds the data, the lookup table 14 outputs the average value for the input data, and the output latch 16 writes the image data to the frame memory 1° or the display memory 2 and displays the image data. Display on device 9.

一例として、3倍の拡大を行なう場合、LUTsに作る
変換テーブルを第3図に示し、空間積和演算回路の演算
子を第4図に示し、説明する。フレームメモリ1の拡大
対象領域の0ライン目をアクセスし、画像データをバッ
ファメモリ3に書込、次にLUT6の変換テーブルを用
い、バッファメモリから画素データを読出、空間積和演
算回路に転送する。この処理を3度繰り返した後、第4
図の演算子を用いて空間積和演算を行ない、フレームメ
モリ1、または表示メモリ2に演算結果を書込む。次に
フレームメモリ1の1ライン目をアクセスし、0ライン
目と同様にバッファメモリに書込、読出、空間積和演算
回路に転送し、フレームメモリの0ライン目2本と1ラ
イン目1本で空間積和演算を行ない、フレームメモリ1
、または表示メモリ2に演算結果を書込む。以下、フレ
ームメモリの0ライン目1本と1ライン目2本の空間積
和演算、1ライン目3本の空間積和演算、1ライン目2
本と2ライン目1本の空間積和演算と繰り返し、画像の
拡大を行なう。
As an example, in the case of three-fold enlargement, a conversion table created in the LUTs is shown in FIG. 3, and an operator of the spatial product-sum calculation circuit is shown in FIG. 4 for explanation. Access the 0th line of the area to be enlarged in frame memory 1, write image data to buffer memory 3, then use the conversion table of LUT 6 to read pixel data from the buffer memory and transfer it to the spatial product-sum calculation circuit. . After repeating this process three times, the fourth
A spatial product-sum operation is performed using the operators shown in the figure, and the operation results are written into the frame memory 1 or the display memory 2. Next, access the 1st line of frame memory 1, write to the buffer memory in the same way as the 0th line, read it, transfer it to the spatial product-sum calculation circuit, and write 2 lines on the 0th line and 1 line on the 1st line of the frame memory. Performs spatial product-sum operation, and stores frame memory 1 in frame memory 1.
, or write the calculation result to the display memory 2. The following is a spatial product-sum calculation for one line on the 0th line and two on the 1st line of the frame memory, a spatial product-sum calculation for three on the 1st line, and a 2nd spatial product on the 1st line.
The spatial product-sum operation for the book and the second line is repeated to enlarge the image.

以上、画像の拡大の手頴を述べたが、空間積和演算回路
4図で示した演算子を用いる場合、第2図の演算子バッ
ファ、および乗算部は必要ないため、より少ない構成で
拡大装置を実現できる。
Above, we have described the steps for enlarging an image. When using the operator shown in Figure 4 of the spatial product-sum operation circuit, the operator buffer and multiplication section in Figure 2 are not required, so the image can be enlarged with fewer configurations. The device can be realized.

発明の効果 以上のように、本発明によれば、補間処理を行なった画
像の拡大、すなわち原画により近い画像拡大を行なうこ
とができる。
Effects of the Invention As described above, according to the present invention, it is possible to enlarge an image that has been subjected to interpolation processing, that is, to enlarge an image closer to the original image.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例における画像拡大装置・・・
・・・フレームメモリ、2・・・・・・表示メモリ、3
・・・・・・バッファメモリ、4・・・・・・アドレス
カウンタ、6・・・・・・ルックアップテーブル(LU
T)、6・・・・・・空間積和演算回路、7・・・・・
・CPU、s・・・・・・セレクタ、9・・・・・・表
示装置。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第2
図 第3図 第4図
FIG. 1 shows an image enlarging device according to an embodiment of the present invention...
...Frame memory, 2...Display memory, 3
...Buffer memory, 4...Address counter, 6...Lookup table (LU
T), 6... Spatial product-sum calculation circuit, 7...
・CPU, s...Selector, 9...Display device. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4

Claims (2)

【特許請求の範囲】[Claims] (1)多階調画像データ(xドット×yライン)を記憶
し、ライン単位にアクセスできるフレームメモリと、画
像データを表示装置に表示するための表示メモリと、ラ
イン毎に転送される画像データを一時記憶しアドレスの
前段にアドレスを操作できるルックアップテーブルを持
つラインバッファメモリを備え、前記ラインバッファメ
モリの書込アドレスと読出アドレスを操作することによ
り画像のライン方向のn倍の拡大を行ない、前記ライン
バッファの出力をn×nの空間積和演算回路で補間処理
を行ない、前記フレームメモリ、あるいは前記表示メモ
リに書込、前記表示装置に出力する画像拡大装置。
(1) A frame memory that stores multi-gradation image data (x dots x y lines) and can be accessed line by line, a display memory that displays image data on a display device, and image data that is transferred line by line. A line buffer memory having a look-up table for temporarily storing and manipulating the address is provided in front of the address, and by manipulating the write address and read address of the line buffer memory, the image is enlarged by n times in the line direction. . An image enlarging device that performs interpolation processing on the output of the line buffer using an n×n spatial product-sum calculation circuit, writes the interpolation process to the frame memory or the display memory, and outputs the result to the display device.
(2)空間積和演算回路は、入力ラッチ、n本の入力ラ
インバッファ、演算子バッファ、乗算部、加算部、ルッ
クアップテーブル、出力ラッチを具備し、前記演算子バ
ッファに記憶する演算子とルックアップテーブルのテー
ブルを選択することにより、n倍拡大の場合はn×n画
素の平均値を出力する特許請求の範囲第1項記載の画像
拡大装置。
(2) The spatial product-sum operation circuit includes an input latch, n input line buffers, an operator buffer, a multiplier, an adder, a look-up table, and an output latch, and includes an operator stored in the operator buffer. 2. The image enlarging apparatus according to claim 1, which outputs an average value of n×n pixels in the case of n-fold enlargement by selecting a look-up table.
JP61251124A 1986-10-22 1986-10-22 Picture enlarging device Pending JPS63104186A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61251124A JPS63104186A (en) 1986-10-22 1986-10-22 Picture enlarging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61251124A JPS63104186A (en) 1986-10-22 1986-10-22 Picture enlarging device

Publications (1)

Publication Number Publication Date
JPS63104186A true JPS63104186A (en) 1988-05-09

Family

ID=17218023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61251124A Pending JPS63104186A (en) 1986-10-22 1986-10-22 Picture enlarging device

Country Status (1)

Country Link
JP (1) JPS63104186A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0410777A2 (en) * 1989-07-28 1991-01-30 Texas Instruments Incorporated Video graphics display memory swizzle logic circuit and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0410777A2 (en) * 1989-07-28 1991-01-30 Texas Instruments Incorporated Video graphics display memory swizzle logic circuit and method

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