DE69027591D1 - Anordnung mit drei Anschlüssen mit veränderlicher Konduktanz - Google Patents

Anordnung mit drei Anschlüssen mit veränderlicher Konduktanz

Info

Publication number
DE69027591D1
DE69027591D1 DE69027591T DE69027591T DE69027591D1 DE 69027591 D1 DE69027591 D1 DE 69027591D1 DE 69027591 T DE69027591 T DE 69027591T DE 69027591 T DE69027591 T DE 69027591T DE 69027591 D1 DE69027591 D1 DE 69027591D1
Authority
DE
Germany
Prior art keywords
terminal arrangement
variable conductance
conductance
variable
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69027591T
Other languages
English (en)
Inventor
Richard A Webb
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE69027591D1 publication Critical patent/DE69027591D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
DE69027591T 1989-12-18 1990-11-02 Anordnung mit drei Anschlüssen mit veränderlicher Konduktanz Expired - Lifetime DE69027591D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/452,186 US5426311A (en) 1989-12-18 1989-12-18 Solid-state variable-conductance device

Publications (1)

Publication Number Publication Date
DE69027591D1 true DE69027591D1 (de) 1996-08-01

Family

ID=23795440

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69027591T Expired - Lifetime DE69027591D1 (de) 1989-12-18 1990-11-02 Anordnung mit drei Anschlüssen mit veränderlicher Konduktanz

Country Status (4)

Country Link
US (1) US5426311A (de)
EP (1) EP0437691B1 (de)
JP (1) JPH0648726B2 (de)
DE (1) DE69027591D1 (de)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5694059A (en) * 1991-12-24 1997-12-02 Hitachi Ltd. Buffer of fine connection structure for connecting an atom level circuit and a general semiconductor circuit
WO2000041245A1 (en) * 1998-12-30 2000-07-13 Alexander Mikhailovich Ilyanok Quantum-size electronic devices and methods of operating thereof
KR100443908B1 (ko) * 2001-10-25 2004-08-09 삼성전자주식회사 플라즈마 화학기상증착장치 및 이를 이용한나이트라이드막 형성방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH559481A5 (de) * 1973-12-13 1975-02-28 Ibm
US4550330A (en) * 1984-06-29 1985-10-29 International Business Machines Corporation Semiconductor interferometer
US4969018A (en) * 1984-07-02 1990-11-06 Texas Instruments Incorp. Quantum-well logic using self-generated potentials
JP2531655B2 (ja) * 1987-01-16 1996-09-04 株式会社日立製作所 半導体装置
US4999682A (en) * 1987-08-14 1991-03-12 Regents Of The University Of Minnesota Electronic and optoelectronic laser devices utilizing light hole properties

Also Published As

Publication number Publication date
JPH0648726B2 (ja) 1994-06-22
JPH03190276A (ja) 1991-08-20
US5426311A (en) 1995-06-20
EP0437691B1 (de) 1996-06-26
EP0437691A1 (de) 1991-07-24

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Legal Events

Date Code Title Description
8332 No legal effect for de