DE68923818T2 - Bidirectional buffer with locking and parity capabilities. - Google Patents

Description

Technical environment of the invention

The present invention relates primarily to circuits for digital signal processing and more particularly to bidirectional receiver/driver buffer circuits comprising a latch and circuitry for both generating and checking parity as a function of the data in the latch.

Background of the invention

Referring first to Fig. 1, there is shown a circuit 10 for bidirectional buffering of digital signals between, for example, first and second signal buses 12, 14. For the sake of explanation, the buses 12, 14 are described as 8-bit data buses.

Circuit 10 comprises eight generally parallel connected bidirectional bit buffer circuits, shown as B0-B7. Bit buffer circuits B0-B7 are identical in construction and only circuit B0 is described and shown in detail here.

Bit buffer circuit B0 comprises two generally parallel bit buffer paths, the first path comprising a receiver 16, a latch 18 and a driver 20 connected in series. In the second of the bit buffer paths, a receiver 22, a latch 24 and a driver 26 are also connected in series, but in the opposite order to the respective components of the first path. The receivers 16, 22 comprise conventional logic bit receivers. The drivers 20, 26 consist of conventional logic bit drivers, each having a control terminal 28 or 30 for selectively setting the output to an active or high-impedance state. The latches 18, 24 comprise conventional transparent latches, each having a control terminal 32 or 34 for selectively setting the latch to a latching or passing (ie transparent) state.

A parity generator 36 is provided, with the inputs of the parity generator connected to the inputs of the receivers 16 in each of the circuits B0-B7. The parity generator 36 comprises a conventional parity "tree" of exclusive-or logic gates. For purposes of illustration, a memory device 38, such as a dynamic random access memory (RAM), is shown connected to the data bus 14.

In operation, circuit 10 generally functions to bidirectionally buffer data between buses 12 and 14. In an example application, buses 12, 14 function as local data buses in a computer system (not shown), with bus 12 connected to the microprocessor and bus 14 connected to memory 38. In accordance with its buffering function, when data is sent from bus 12 to bus 14, an appropriate signal is applied to control terminal 30 such that driver 26 is placed in a high impedance state. Data in the form of a logic HIGH or LOW of bit 0 is sampled by receiver 16 and converted to another logic level (i.e., 1 or 0). Receiver 16 thus operates in a standard mode of operation to convert a wide range of input signals to a narrower range of output signals. A signal is applied to the control terminal 32 to latch or pass bit 0 in the latch 18. The data at the output of the latch 18 is then sampled by the driver 20, which is controlled via the terminal 28 to go into the active mode for driving bus 14. The data is transferred in basically the same way from bus 14 to bus 12 via the path that connects the receiver 22, latch 24, and driver 26. Parity generator 36 has the capability of generating a parity bit corresponding to the data on bus 12. When such parity generation is required, the data on bus 12 is frozen for a period of time sufficient to allow parity generator 36 to process the data and generate the parity bit. Parity generator 36 also has the capability of generating a parity bit corresponding to the data on bus 14, with the data either latched in or passed through latch 24.

When applied in a computer environment as described above, circuit 10 presents the fundamental disadvantage that data transfer on bus 12 is interrupted whenever it is found necessary for a parity bit to be generated. More specifically, when parity satisfying the data on bus 12 is generated, the data on bus 12 must be frozen for a period of time sufficient for parity generator 36 to operate. In the same way, the data on bus 14 must be frozen or latched in buffer 24 whenever it is necessary to generate a parity bit satisfying the data on bus 14. In either of these states, the data is present at the output of driver 26, and it is thus necessary to interrupt data transfer on bus 12.

Summary of the invention

It is a fundamental object of the invention to provide an arrangement for buffering and parity checking digital data transferred between two data buses, which allows a parity to be generated which satisfies the data without interrupting either of the data buses.

It is a further object of the present invention to provide such an arrangement which provides new and improved buffers and driver circuits that enable increased operating speed.

A further object of the invention is to provide a truly transparent circuit for a buffer, which in turn enables buffering of data without introducing a significant delay between the input and output elements.

It is a further object of the present invention to provide a driver comprising a phase splitting circuit which enables the driver to achieve increased speed and does not require a significant increase in power requirements.

These objects are achieved by the structure as described in the claims.

Short description of the drawings

These and other objects, features and advantages of the invention will become apparent upon consideration of the following description and the drawings, which illustrate:

Fig. 1 is a block diagram of a buffer and parity generation circuit constructed in accordance with the prior art and described herein;

Fig. 2 is a block diagram of a buffer and parity generation circuit constructed in accordance with the present invention; and

Fig. 3A is a circuit diagram of the receiver and latch circuits of Fig. 2 implemented in bipolar transistor logic.

Fig. 3B is a circuit diagram of a driver circuit according to Fig. 2, which was implemented in bipolar transistor logic;

Fig. 4 is a block diagram of a transparent latch circuit constructed in accordance with the prior art; and

Figure 5 is a simplified block diagram illustrating the logical connections of the transparent latch circuit constructed in accordance with the present invention.

Detailed description of the invention

Referring to Figure 2, a circuit 50 constructed in accordance with the present invention consists of eight bidirectional bit buffer circuits C0-C7 connected between a pair of data buses 52, 54 and a parity generating and checking circuit 56. The circuits C0-C7 may be of the same construction, each bidirectionally buffering a single bit line (not shown) between the buses 52, 54. For purposes of illustration, only circuit C0 is shown and described in detail.

Circuit C0 includes two data paths connected in parallel, the first path having a receiver 57, a latch 58 and a driver 60 connected in series between buses 52 and 54, respectively. The second data path in circuit C0 includes a receiver 62, a latch 64 and a driver 66 connected in series between buses 54 and 52, respectively. Drivers 60, 66 each include a terminal 61 and 67, respectively, for setting their outputs to either an active or high impedance state. Latches 58, 64 each include a control terminal 59 and 63, respectively, for selectively latching or passing the data at their inputs. Preferred embodiments of these components are described below.

Continuing the description of Fig. 2, a parity generating circuit 68 is connected to the output of latch 58 of circuit C0 and to the output of the associated latch in circuits C1-C7. Thus, parity generator 68 serves to generate a parity bit for the data at the outputs of the latches. Parity generator 68 preferably comprises an exclusive-OR tree of the type shown in IBM Technical Disclosure Bulletin Volume 16, No. 10, page 3249.

Parity generator 68 has its outputs connected to both the input of parity driver circuit 70 and the input of exclusive NOR gate 72. Parity driver circuit 70 includes a control terminal 73 for selecting an active controlled or high impedance output state, this control terminal being connected to the output of a gen/chk (i.e., parity generation or checking) receiver 74 and an enable terminal 76 on gate 72. A parity receiver 78 has an input 79 connected in common to the output of parity driver 70 and an output connected to a second input of gate 72.

An error driver 80 has its inputs connected to the output of gate 72. For convenience, a memory device 84, such as dynamic random access memory, is shown connected to bus 54. Gate 72, receivers 74, 78 and drivers 70, 80 comprise conventional circuitry.

In operation, circuit 50 can be operated to generate parity of data on one of the buses 52, 54 by applying appropriate signals to the latch control terminals 59, 63, the driver control terminals 61, 67, 73 and the inputs of the receivers 74, 78 without interrupting the operation of the buses. Circuit 50 can also be used to check data on one of the buses against a stored parity bit. Considering the operation of circuit 50 as described below, Readers will find many useful functions related to buffering and parity.

For the sake of clarity, the operation of circuit 50 will now be described with reference to the block diagram of Fig. 2. First, the operation of circuit 50 necessary to generate a parity bit for the data on bus 52 and to place the parity bit and associated data on bus 54 will be described. To perform this function, control terminal 59 is controlled to hold the data on bus 52 in latch 58, leaving bus 52 free for subsequent data transfer. Driver 60 is controlled via terminal 61 to assume its high impedance state when it is necessary to otherwise hold bus 54 active and to assume its active driving state when it is necessary to place the latched data on the bus. Gen/chk receiver 74 is controlled to disable gate 72. Parity generator 68 operates to generate at its output a parity bit for the bits available at the input of drivers 60 in circuits C0-C7. This parity bit is made available at output 79 of parity receiver 78. Thus, in accordance with the primary advantage of the present invention, the parity of data on bus 52 is generated and made available with the data without interrupting the operation of either bus 52 or 54.

When it is necessary to check the parity of data on bus 52 against a previously generated and stored parity bit (e.g., stored in memory 84), circuit 50 is operated in a manner identical to that described above except that gen/chk receiver 74 is operated to enable gate 72 and disable parity driver 70. The stored parity bit is applied to input terminal 79 of parity receiver 78 and compared with the output of parity generator 68 at gate 72. If the stored parity bit does not match the newly generated parity bit, an error signal, e.g., a logical Zero, applied to the output of error driver 80.

Next, the operation of circuit 50 for generating and controlling the parity of the data on bus 54 will be described. To effect this operation, control port 63 is operated to place latch 64 in the transparent mode. Driver 66 is placed in its active state and control port 59 is operated to hold the data from bus 54 in latch 58. Once the data from bus 54 is held in latch 58, control ports 61, 67 of drivers 60, 66 are operated to clear buses 52, 54 for further data transfers. Gen/chk receiver 74 is operated to place circuit 56 in the parity generating mode as described above. When operated in this way, a parity data bit for the data on bus 54 is generated by parity generator 68 and made available at terminal 79. The associated data is made available via the output of latch 58 and can be read on bus 54 via driver 60 or on bus 52 via driver 60, receiver 62, latch 64 and driver 66. This is to be understood as meaning that parity for the data on bus 54 can be generated without having to interrupt the transmission of data on either bus 52 or 54.

The parity of data on bus 54 can be checked against a stored parity bit by operating circuit 50 in a manner identical to that described above, except that gen/chk receiver 74 is operated in a manner such that parity driver 70 is disabled (i.e., placed in the high impedance state) and gate 72 is placed in the active mode and then the data is checked.

It can thus be seen that by appropriately controlling the buffers and drivers in circuit 50, the parity for the data on the buses 52, 54 can be generated and checked without stopping the data transfer on the buses. It is understandable that for many data transfers it is necessary is to keep both data buses 52, 54 free during the generation and checking of parity. For example, if bus 52 is waiting for data from bus 54, it is not necessary to keep bus 52 in the uninterrupted state. Under such circumstances, parity can be generated or checked without latching data in latches 58, 64. For such a data transfer from bus 54 to bus 52, latches 58, 64 can be placed in the transparent mode and driver 66 in its active state. The data is then held on bus 54 for a time sufficient for parity generator 68 to perform its function. Parity generator 68 then generates a parity bit for the data on bus 54 and makes the parity bit available at output terminal 79 with the data to driver 66.

It will be appreciated that depending on the data transfer and parity generation/checking requirements, circuit 50 may be operated to perform a variety of functions. Other such functions not described above are set forth below in Table 1, where: X indicates that the controllable state of a component is irrelevant, Hi-Z indicates a high impedance state for a driver, and the remainder of the description is self-explanatory from the above considerations. Table 1 Cache Driver active Parity function Parity check of data on bus Parity generation of data on bus

Referring now to Fig. 3, preferred embodiments the receivers 57, 62, latches 58, 64 and drivers 60, 66. For the sake of explanation, the reference numbers from the first set of components are used. It will be appreciated that latches 58 and drivers 60 contain and consist of significant inventions.

Recipient

In describing the first receiver 57, a transistor T2 has an input terminal 90 connected to its collector and a shorted base-emitter junction connected to the base of a transistor T4. A supply voltage, designated throughout as Vcc, is applied to the base of T4 through a resistor R2 and to the collector of the transistor through a resistor R4. The base of transistor T4 is grounded to circuit ground through a capacitor C2.

Continuing the description of receiver 57, the emitter of transistor T4 is connected to the base of transistor T6, the emitter of the latter transistor being connected to the collector of a transistor T8. Transistor T8 has its collector-base junction shorted and both transistors T6 and T8 have Schottky diodes D2 and D4 respectively connected across their base-collector junctions. A resistor R6 is connected between the base of transistor T6 and the collector of transistor T8, and a resistor R8 is connected between the collector of transistor T8 and ground. The voltage supply Vcc is applied to the collector of transistor T6 through a resistor R10.

During operation, when a logic 0 is applied to the collector terminal 90 of transistor T2, T2 produces a voltage drop like a diode. At standard TTL logic levels (ie, logic LOW/0 = 0.6 V, logic HIGH/1 = 2.4 V, Vcc =5 V), the emitter of transistor T2 is one diode voltage drop above the collector, or about 1.4 V. The emitter of transistor T4 is two diode voltage drops above Ground, and the transistor thus remains in the off state. The collector of transistor T6, shown here as node A, is at logic 1. When a logic 1 is applied to receiver 57 at terminal 90, the emitter of transistor T2 is at a voltage sufficient to turn on transistors T4, T6 and T8, bringing node A to logic 0. It can thus be seen that the "output" of receiver 57, ie the logic level at node A, is the inverse level of the input of terminal 90.

Cache

Referring now to Figures 4 and 5 and additionally to Figure 3, Figure 4 shows a simplified block diagram of a prior art "transparent" latch 94 connected to, for example, a receiver 92 and a driver 96. Although the latch can be enabled to pass the data without holding it (hence the term "transparent"), it still includes transistors (not shown) in series between the input device (receiver 92) and the output device (driver 96). Even when latch 94 is operated in pass mode, these transistors introduce a non-negligible delay in the data.

Referring now to Figure 5, a simplified block diagram of receiver 57, latch 58, and driver 60 illustrates that with the latch of the present invention, no transistors are placed between the input (receiver 57) and the output (driver 60) of the latch. Receiver 57, latch 58, and driver 60 are effectively T-connected to node A. Therefore, latch 58 does not introduce any significant delay in the signal path between receiver 57 and driver 60.

Referring now to Fig. 3, latch 58 comprises a transistor T10 whose collector is connected to the base of transistor T6 A Schottky diode D6 is connected across the base-collector junction of transistor T10. The emitter of transistor T10 is connected in parallel with the collector of transistor T8 and connected to ground through a capacitor C4. The base of transistor T10 is connected to a transistor T12 through a pair of series-connected resistors R12, R14, the junction of the resistors having a control terminal shown at 98. The base of transistor T12 is connected to the collector of a transistor T14 and its emitter is connected together with the emitter of transistor T14 to the shorted base-emitter junction of a transistor T16. The Schottky diodes D8, D10 and D12 are connected across the base-collector junctions of transistors T12, T16 and T14 respectively. The collector/cathode junction of transistor T6 and diode D10 is connected to ground, and the base of transistor T14 is connected to circuit node A via a resistor R16.

In operation, a logic HIGH signal is applied to terminal 98 to activate latch circuit 58 and thus hold the logic signal present at node A. First, latching a logic 0 at node A will be described with control terminal 98 LOW, transistors T4 and T6 turned on, and therefore node A pulled to a logic LOW state and transistor T14 turned off. When a logic HIGH signal is applied to terminal 98, transistors T10 and T12 turn on, the collector of transistor T10 is pulled to a logic LOW state, and transistor T6 is turned off. Node A is thus latched in a logic LOW (or 0) state regardless of any change at the input terminal 90 of receiver 57.

In the following description of latching a logic 1 at node A when control terminal 98 is at a logic LOW, T6 is off and T14 is on. T12 and T10 are off. Thus, the voltage at node A represents a logic HIGH. When a logic HIGH signal is present at terminal 98 is applied to enable the latch, transistor T14 holds transistor T12 off. However, transistor T10 is on, holding transistor T6 off. With transistors T12 and T6 off, node A is held at logic HIGH regardless of the inputs to receiver 57 at terminal 90.

It can thus be seen that the basic function of holding the latch circuit 58 is affected by the above-described connection of transistors T12, T14 as they are controlled by the signal applied to terminal 98 to hold the logic signal at node A. Transistor T16 acts solely as diode D10 to raise the emitters of transistors T12, T14 above ground by a Schottky diode voltage drop. Transistor T10 serves to provide a signal to its collector to feed back to receiver 57 and disable it, thus preventing any change at the receiver's input 90 from appearing at node A.

driver

Referring now to Fig. 3B, a new inventive circuit arrangement for driver 60 is shown, the circuit basically consisting of seven functional components: a phase splitter 100, an impedance controller 102 (shown in two separate blocks), a HIGH level driver 104, a HIGH level driver 106, a high level DC clamp 108, a beta degradation clamp 100, and an overshoot clamp 112. For convenience of description, the functional components of driver 60 are basically described as indicated below.

Phase splitter

When examining the phase splitter 100, it can be seen that the base of a transistor T20 is connected to the emitter of a transistor T22, which connection is connected to circuit node A (Fig. 3A). A pair of Schottky diodes D20, D22 are connected across the base-collector junctions of transistors T20, T22, respectively. As will be described in more detail below, it is this new and improved arrangement of phase splitter 100 that provides a driver 60 with improved speed at comparable power compared to prior art drivers.

HIGH level driver

The collector of transistor T20 is connected to the base of transistor T24 in a HIGH level driver circuit 104 to apply the voltage Vcc through a resistor R20. The collector of transistor T24 is connected to the supply voltage Vcc through a resistor R22 and to the collector of a transistor T26. The emitter of transistor T24 is connected to the base of transistor T26.

LOW level driver

The base of transistor T22 in phase splitter 100 is connected through a pair of series connected resistors R24, R26 to the collector of a transistor T28 in a LOW level driver 106, the junction of the resistors being connected to the supply voltage Vcc. The collector of transistor T22 is connected to the base of transistor T28 and the emitter of the latter transistor is connected to circuit ground through a resistor R28. The base of transistor T28 is connected to the collector of a transistor T30 through a capacitor C20. The base of transistor T30 is connected to the emitter of transistor T28 and the emitter of transistor T26 through a Schottky diode D24. The emitter of transistor T30 is connected directly to circuit ground.

Impedance control unit

Impedance control unit 102 comprises two circuit parts. The first part comprises a pair of transistors T32, T34, whose collector-emitter paths are connected in series between the collector of transistor T22 and ground. The base-emitter junction of transistor T34 is bridged in parallel with a Schottky diode D26. A Schottky diode D28 is connected across the base-collector junction of transistor T32, with a control terminal 120 connected to the base of the transistor via a resistor R30. This part of the circuit operates with the LOW level circuit 106, as described in more detail below.

A second part of the impedance control circuit 102 includes a pair of transistors T36, T38 and a pair of Schottky diodes D30, D32. These components are connected in an identical arrangement to the transistors T32, T34 and the diodes D32 and D34, respectively, as described above, except that they are connected together to operate with the HIGH level circuit 104. Accordingly, the collector of transistor T36 is connected in common with the base of transistor T24 to the collector of transistor T20. The base of transistor T38 is connected to the emitter of transistor T20 and the emitter of transistor T38 is connected to ground.

DC clamping

DC clamp circuit 108 includes a single transistor T40, the collector of which is connected to the base of transistor T24 through a resistor R32. A Schottky diode D36 is connected across the base-collector junction of transistor T40, with the anode of diode D36 connected to circuit ground through a resistor R34. The base of transistor T40 is further connected to the emitter of transistor T24 through a resistor R36. The emitter of transistor T40 is connected to circuit ground.

Overshoot clamping

The overshoot clamp 112 comprises a transistor T42, the collector and base of which are connected to the collector and base of transistor T24, respectively. A Schottky diode D38 is connected across the collector-base junction of transistor T42, and the transistor has its emitter connected to the base of a transistor T44 through a resistor R40. The emitter of transistor T44 is connected to circuit ground, and the collector of the transistor is connected to the emitter of a transistor T46. A pair of resistors R42, R44 are connected in series between the emitter and collector of transistor T46, the junction of the resistors being connected to the base of the transistor. The collector of transistor T46 is connected to a terminal 122, the terminal comprising the output terminal for driver 60.

Beta degradation clamp 110

The beta degradation clamp 110 comprises a transistor T48, which has its emitter connected to the emitter of transistor T24 and the base of transistor T26. The base-collector junction of transistor T48 is short-circuited and connected to the emitter of a transistor T50. A Schottky diode D40 is connected across the base-collector junction of transistor T50, with the base of the transistor connected to the emitters of a transistor pair T52, T54. The base-collector junction of transistor T52 is short-circuited and connected to the emitter of transistor T26. The base-emitter junction of transistor T54 is short-circuited. A Schottky diode D41 is connected across the base-collector junction of transistor T54, with the collector of the transistor connected to the emitter of transistor T26 and to terminal 122. The emitter of a transistor T55 is connected to the collector of transistor T50, and a shorted base-collector junction is connected to the supply voltage Vcc.

Driver operation

During operation, the output signal of driver 60 at terminal 122 is opposite to the logic input signal at node A, with compensation for the signal inversion in receiver 57 being carried out as described above.

First, the control of a logic LOW output signal at terminal 122 is described, where the logic input signal at node A is HIGH. The HIGH input signal at node A turns on transistors T20 and T38. Transistors T24 and T26 in the HIGH level driver circuit 104 are turned off. Transistor T22 turns off and diode D22 turns on, turning on transistors T28, T30 in the LOW level driver circuit 106. The collector of transistor T30 pulls the output terminal 122 to a logic LOW level.

Next, the driving of a logic HIGH output signal at terminal 122 is described, with the logic input signal at node A being LOW. Transistors T20 and T38 turn off and transistor T22 turns on, turning off transistors T28 and T30 in LOW level driver circuit 106. Transistors T24 and T26 in HIGH level driver circuit 104 turn on. Thus, the emitter of transistor T26 sets output terminal 122 to a logic HIGH signal level. Capacitor C20 controls the rate of change between the logic HIGH and LOW levels at output terminal 122.

The basic operation has been described above, while the operation of the various clamping and control circuits is now described.

The beta degradation clamp circuit 110 operates to prevent excessive bias voltage from developing across the emitter-base junction of transistor T12 and thus degrading the beta of the transistor. During operation the transistors T48, T50 and T52 act as diode voltage drops, while the transistors T50 and T55 provide the current flow that is conducted through the resistors R34, R36. The potential at the base of T26 is thus raised to limit the blocking voltage.

DC clamp circuit 108 acts as a conventional Baker clamp to limit the maximum voltage of a logic HIGH signal at output terminal 122. In operation, when T24 is turned on by applying a logic LOW to node A, resistors R36, R34 and transistor T40 act to limit the base current of transistor T24.

The overshoot clamp circuit 112 serves to limit excessive ringing and thus calm a logic HIGH signal at output terminal 122. During operation, transistors T42, T44 are on when a logic LOW signal is present at node A. When excessive ringing occurs, T46 turns on, lowering the current at terminal 122 and thus calming the signal at the terminal.

Finally, when a logic HIGH control signal is applied to terminal 120, impedance control circuit 102 serves to place the output signal from terminal 122 of driver 60 in a high impedance state. During operation, when a logic HIGH signal is applied to terminal 120, transistors T36 and T38 turn on and hold transistor T26 in HIGH level driver circuit 104 off. At the same time, transistors T32, T34 turn on and hold transistors T28, T30 in LOW level driver circuit 106 off. Terminal 122 thus presents a high impedance to any controlled load (not shown).

In summary, the operation of the driver circuit 60 with the new and improved phase splitter circuit 100 can be understood to provide substantially increased speed at comparable power consumption.

There has thus been provided a new and improved electronic circuit for buffering and parity checking digital data transferred between data buses. The circuit prevents parity generation and checking from being performed without substantial interruption of data transmission on either bus. The circuit is very flexible in nature, allowing, through an associated control unit, a wide variety of parity generation and checking functions to be performed. The circuit is particularly applicable to buffering and parity checking data transferred between data buses in computers. When implemented using the preferred embodiments of the receiver, buffer and driver components described above, the circuit provides the advantage of being very fast while consuming an acceptable amount of power.

While the present invention has been described with reference to a particular embodiment, it will be understood that the invention is not limited. For example, while the preferred embodiments of the receiver, latch and driver circuits as shown have been implemented in TTL logic using NPN bipolar transistors, these circuits can be implemented in the same manner using other types of logic, such as PNP bipolar transistors or field effect transistors (FETs).

Claims (8)

1. Device for buffering and parity checking digital data transmitted between a first and a second data bus, comprising: a plurality of bidirectional buffer circuits, and each of the bidirectional bit buffer circuits comprises, a first data path comprising a first receiver, which has an input connected to the first data bus and an output connected to a first circuit node, means for buffering, which have a connection connected to the first circuit node for selectively holding data at the first circuit node, and a first driver, which has an input connected to the first circuit node and an output connected to the second data bus, a second data path comprising a second receiver having an input directly connected to the first data bus and the first data driver and an output connected to a second circuit node, means for buffering, having a terminal connected to the second circuit node for selectively holding data at the second circuit node, and a driver having an input connected to the second circuit node and an output cross-connected to the first data bus and the first receiver, Means for controlling the driver for selectively setting the output of the first driver to a actively driving or high-impedance state and means for controlling the data latches for selectively holding data at the associated first or second circuit node, or for preventing the output of the receiver at the associated first or second circuit node from changing the data at the associated first or second circuit node, and parity generating means connected to the circuit node of the first path in each of the bidirectional bit buffer circuits for generating a parity signal with respect to the data at the circuit node of the first circuit node. 2. Apparatus according to claim 1, further including error detection means connected to the output of the parity generating means for comparing the parity signal with a second parity signal and generating an error signal if the two parity signals are not identical. 3. Device according to claim 2, wherein the means for error detection consist of the following: a logic exclusive-OR gate having a first input connected to the output of the parity generator; and Means for applying the second parity signal to a second input of the exclusive-OR gate. 4. Device according to claim 3, wherein the means for applying the second parity signal consist of the following: a parity terminal for receiving the second parity signal; a parity receiver which has its input connected to the first parity terminal and its output connected to the second input of the logical exclusive-or gate; and a parity driver having an input connected to the output of the parity generating means and an output connected to the parity terminal. 5. The apparatus of claim 4, wherein the means for applying the second parity signal further comprises a control receiver having an output connected to both the control terminal of the parity driver and the enable terminal of the exclusive-OR gate. 6. The apparatus of claim 1, wherein each of the drivers has a phase splitting circuit connected to its associated receiver and a latch at a first or second circuit node. 7. The apparatus of claim 1, wherein the latch circuit in each of the data paths further comprises means connected to the receiver in the data path for disabling the receiver when the latch is instructed to hold the data at the associated first or second circuit node. 8. Device according to claims 1 to 7, which is used in a computer, which comprises first and second data buses for the transmission of the data, wherein the Apparatus for buffering and parity checking digital data transmitted between first and second data buses, comprising: a plurality of bidirectional buffer circuits, and each of the bidirectional bit buffer circuits comprises, a first data path comprising a first receiver, which has an input connected to the first data bus and an output connected to a first circuit node, means for buffering, which have a connection connected to the first circuit node for selectively holding data at the first circuit node, and a first driver, which has an input connected to the first circuit node and an output connected to the second data bus, a second data path comprising a second receiver having an input directly connected to the first data bus and the first data driver and an output connected to a second circuit node, means for buffering, having a terminal connected to the second circuit node for selectively holding data at the second circuit node, and a driver having an input connected to the second circuit node and an output cross-connected to the first data bus and the first receiver, Means for controlling the driver for selectively setting the output of the first driver to an active driving or high-impedance state and Means for controlling the data buffers for selectively holding data at the associated first or second circuit node, or preventing the output of the receiver at the associated first or second circuit node from changing the data at the associated first or second circuit node, and parity generating means connected to the circuit node of the first path in each of the bidirectional bit buffer circuits for generating a parity signal with respect to the data at the circuit node of the first circuit node.