DE68923666D1 - Staffelverfahren zur Ausführung von verschachtelten Schleifen in Mehrprozessorrechnern. - Google Patents

Staffelverfahren zur Ausführung von verschachtelten Schleifen in Mehrprozessorrechnern.

Info

Publication number
DE68923666D1
DE68923666D1 DE68923666T DE68923666T DE68923666D1 DE 68923666 D1 DE68923666 D1 DE 68923666D1 DE 68923666 T DE68923666 T DE 68923666T DE 68923666 T DE68923666 T DE 68923666T DE 68923666 D1 DE68923666 D1 DE 68923666D1
Authority
DE
Germany
Prior art keywords
processor
iterations
outer loop
assigned
iteration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923666T
Other languages
English (en)
Other versions
DE68923666T2 (de
Inventor
Kevin W Harris
William B Noyce
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE68923666D1 publication Critical patent/DE68923666D1/de
Application granted granted Critical
Publication of DE68923666T2 publication Critical patent/DE68923666T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/45—Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451—Code distribution
    • G06F8/452—Loops

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Multi Processors (AREA)
  • Complex Calculations (AREA)
DE68923666T 1988-07-29 1989-06-22 Staffelverfahren zur Ausführung von verschachtelten Schleifen in Mehrprozessorrechnern. Expired - Fee Related DE68923666T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US22625788A 1988-07-29 1988-07-29

Publications (2)

Publication Number Publication Date
DE68923666D1 true DE68923666D1 (de) 1995-09-07
DE68923666T2 DE68923666T2 (de) 1996-03-21

Family

ID=22848179

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923666T Expired - Fee Related DE68923666T2 (de) 1988-07-29 1989-06-22 Staffelverfahren zur Ausführung von verschachtelten Schleifen in Mehrprozessorrechnern.

Country Status (6)

Country Link
US (1) US5481723A (de)
EP (1) EP0352899B1 (de)
JP (1) JPH0298741A (de)
AT (1) ATE125966T1 (de)
CA (1) CA1319757C (de)
DE (1) DE68923666T2 (de)

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JPH04155576A (ja) * 1990-10-19 1992-05-28 Fujitsu Ltd コンパイル処理方式
JP2921190B2 (ja) * 1991-07-25 1999-07-19 日本電気株式会社 並列実行方式
US5802375A (en) * 1994-11-23 1998-09-01 Cray Research, Inc. Outer loop vectorization
JP2669603B2 (ja) * 1994-12-15 1997-10-29 インターナショナル・ビジネス・マシーンズ・コーポレイション コンパイラにおけるコード生成方法及びコンパイラ
US5710913A (en) * 1995-12-29 1998-01-20 Atmel Corporation Method and apparatus for executing nested loops in a digital signal processor
GB2323190B (en) * 1997-03-14 2001-09-19 Nokia Mobile Phones Ltd Executing nested loops
US6301706B1 (en) * 1997-12-31 2001-10-09 Elbrus International Limited Compiler method and apparatus for elimination of redundant speculative computations from innermost loops
US6106575A (en) * 1998-05-13 2000-08-22 Microsoft Corporation Nested parallel language preprocessor for converting parallel language programs into sequential code
US6292822B1 (en) 1998-05-13 2001-09-18 Microsoft Corporation Dynamic load balancing among processors in a parallel computer
US6192515B1 (en) * 1998-07-17 2001-02-20 Intel Corporation Method for software pipelining nested loops
US6269440B1 (en) * 1999-02-05 2001-07-31 Agere Systems Guardian Corp. Accelerating vector processing using plural sequencers to process multiple loop iterations simultaneously
CA2288614C (en) * 1999-11-08 2004-05-11 Robert J. Blainey Loop allocation for optimizing compilers
US7337437B2 (en) * 1999-12-01 2008-02-26 International Business Machines Corporation Compiler optimisation of source code by determination and utilization of the equivalence of algebraic expressions in the source code
JP3477137B2 (ja) * 2000-03-03 2003-12-10 松下電器産業株式会社 最適化装置及び最適化プログラムを記録したコンピュータ読み取り可能な記録媒体
US8176108B2 (en) * 2000-06-20 2012-05-08 International Business Machines Corporation Method, apparatus and computer program product for network design and analysis
US7278137B1 (en) 2001-12-26 2007-10-02 Arc International Methods and apparatus for compiling instructions for a data processor
US7210128B2 (en) * 2002-10-14 2007-04-24 Fujitsu Limited Event-driven observability enhanced coverage analysis
US7089545B2 (en) * 2002-12-17 2006-08-08 International Business Machines Corporation Detection of reduction variables in an assignment statement
US7171544B2 (en) * 2003-12-15 2007-01-30 International Business Machines Corporation Run-time parallelization of loops in computer programs by access patterns
KR100806274B1 (ko) * 2005-12-06 2008-02-22 한국전자통신연구원 멀티 쓰레디드 프로세서 기반의 병렬 시스템을 위한 적응형실행 방법
US7926046B2 (en) * 2005-12-13 2011-04-12 Soorgoli Ashok Halambi Compiler method for extracting and accelerator template program
KR100681199B1 (ko) * 2006-01-11 2007-02-09 삼성전자주식회사 코어스 그레인 어레이에서의 인터럽트 처리 방법 및 장치
US8291396B1 (en) * 2006-01-17 2012-10-16 Altera Corporation Scheduling optimization of aliased pointers for implementation on programmable chips
US8443351B2 (en) * 2006-02-23 2013-05-14 Microsoft Corporation Parallel loops in a workflow
JP5102576B2 (ja) * 2007-10-10 2012-12-19 Ｎｏｋ株式会社 アキュムレータ
KR100907530B1 (ko) * 2008-01-25 2009-07-14 최성수 높이 조절이 가능한 보조 난간
US8572359B2 (en) 2009-12-30 2013-10-29 International Business Machines Corporation Runtime extraction of data parallelism
US9696995B2 (en) * 2009-12-30 2017-07-04 International Business Machines Corporation Parallel execution unit that extracts data parallelism at runtime
US8683185B2 (en) 2010-07-26 2014-03-25 International Business Machines Corporation Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
US9430204B2 (en) 2010-11-19 2016-08-30 Microsoft Technology Licensing, Llc Read-only communication operator
US9507568B2 (en) * 2010-12-09 2016-11-29 Microsoft Technology Licensing, Llc Nested communication operator
US9395957B2 (en) 2010-12-22 2016-07-19 Microsoft Technology Licensing, Llc Agile communication operator
JP5714622B2 (ja) * 2013-02-21 2015-05-07 トヨタ自動車株式会社 制御装置
US20150268993A1 (en) * 2014-03-21 2015-09-24 Qualcomm Incorporated Method for Exploiting Parallelism in Nested Parallel Patterns in Task-based Systems
DE102017209697A1 (de) * 2016-06-13 2017-12-14 Denso Corporation Parallelisierungsverfahren, Parallelisierungswerkzeug und fahrzeuginterne Vorrichtung
WO2021070322A1 (ja) * 2019-10-10 2021-04-15 日本電信電話株式会社 秘密多重反復計算装置、方法及びプログラム

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4468736A (en) * 1982-06-08 1984-08-28 Burroughs Corporation Mechanism for creating dependency free code for multiple processing elements
US4829427A (en) * 1984-05-25 1989-05-09 Data General Corporation Database query code generation and optimization based on the cost of alternate access methods
US4794521A (en) * 1985-07-22 1988-12-27 Alliant Computer Systems Corporation Digital computer with cache capable of concurrently handling multiple accesses from parallel processors
US4710872A (en) * 1985-08-07 1987-12-01 International Business Machines Corporation Method for vectorizing and executing on an SIMD machine outer loops in the presence of recurrent inner loops
JPH0814817B2 (ja) * 1986-10-09 1996-02-14 株式会社日立製作所 自動ベクトル化方法
US5093916A (en) * 1988-05-20 1992-03-03 International Business Machines Corporation System for inserting constructs into compiled code, defining scoping of common blocks and dynamically binding common blocks to tasks

Also Published As

Publication number Publication date
CA1319757C (en) 1993-06-29
EP0352899A1 (de) 1990-01-31
EP0352899B1 (de) 1995-08-02
JPH0298741A (ja) 1990-04-11
ATE125966T1 (de) 1995-08-15
DE68923666T2 (de) 1996-03-21
US5481723A (en) 1996-01-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee