DE68923549D1 - Dekodierringanordnung. - Google Patents

Dekodierringanordnung.

Info

Publication number
DE68923549D1
DE68923549D1 DE68923549T DE68923549T DE68923549D1 DE 68923549 D1 DE68923549 D1 DE 68923549D1 DE 68923549 T DE68923549 T DE 68923549T DE 68923549 T DE68923549 T DE 68923549T DE 68923549 D1 DE68923549 D1 DE 68923549D1
Authority
DE
Germany
Prior art keywords
ring arrangement
decoding ring
decoding
arrangement
ring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE68923549T
Other languages
English (en)
Other versions
DE68923549T2 (de
Inventor
William Shumate
Daniel Kindred
Franklin Antonio
Steven Gardner
Krishnanand Kelkar
Thomas Bilotta
Steven Rogers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Engility LLC
Original Assignee
Titan Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Titan Corp filed Critical Titan Corp
Application granted granted Critical
Publication of DE68923549D1 publication Critical patent/DE68923549D1/de
Publication of DE68923549T2 publication Critical patent/DE68923549T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Error Detection And Correction (AREA)
  • Small-Scale Networks (AREA)
  • Bus Control (AREA)
DE68923549T 1988-03-10 1989-02-28 Dekodierringanordnung. Expired - Fee Related DE68923549T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/166,187 US4879720A (en) 1988-03-10 1988-03-10 Decoder ring system
PCT/US1989/000815 WO1989008884A1 (en) 1988-03-10 1989-02-28 Decoder ring system

Publications (2)

Publication Number Publication Date
DE68923549D1 true DE68923549D1 (de) 1995-08-24
DE68923549T2 DE68923549T2 (de) 1996-01-04

Family

ID=22602171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE68923549T Expired - Fee Related DE68923549T2 (de) 1988-03-10 1989-02-28 Dekodierringanordnung.

Country Status (5)

Country Link
US (1) US4879720A (de)
EP (1) EP0403566B1 (de)
JP (1) JPH03504309A (de)
DE (1) DE68923549T2 (de)
WO (1) WO1989008884A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5010558A (en) * 1988-09-29 1991-04-23 Harris Corporation Data overlap decoder
US5414857A (en) * 1992-10-02 1995-05-09 Ast Research, Inc. Adaptive processor interface operable with different types of processors
FR2730883B1 (fr) * 1995-02-17 1997-04-04 Alcatel Telspace Dispositif d'initialisation d'un decodeur de viterbi compris dans un recepteur de signaux transmis sous forme de paquets emetteur, recepteur et procede correspondants
US7231008B2 (en) * 2002-11-15 2007-06-12 Vitesse Semiconductor Corporation Fast locking clock and data recovery unit
JP4900800B2 (ja) * 2003-07-02 2012-03-21 エスティー‐エリクソン、ソシエテ、アノニム 複数のシフト・レジスタ機能を有するシングル・メモリ
TWI351182B (en) * 2008-02-22 2011-10-21 Ralink Technology Corp Power-saving method for use with viterbi decoder and bit processing circuit of wireless receiver
US8483344B2 (en) 2011-06-13 2013-07-09 Stephen C. Dillinger Fast lock serializer-deserializer (SERDES) architecture

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3665396A (en) * 1968-10-11 1972-05-23 Codex Corp Sequential decoding
US3657700A (en) * 1970-07-13 1972-04-18 American Computer Commun Forward error correcting system
US4677625A (en) * 1985-03-01 1987-06-30 Paradyne Corporation Distributed trellis encoder

Also Published As

Publication number Publication date
WO1989008884A1 (en) 1989-09-21
DE68923549T2 (de) 1996-01-04
EP0403566B1 (de) 1995-07-19
US4879720A (en) 1989-11-07
EP0403566A4 (en) 1992-01-22
EP0403566A1 (de) 1990-12-27
JPH03504309A (ja) 1991-09-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee