DE60320279T2 - METHOD AND SYSTEM FOR INTEGRATING A MATCHING DRIVER TO THE MAIN LOOP OF A DELTA SIGMA MODULATOR - Google Patents

Abstract

A method and system for integrating a mismatch noise shaper into the main loop of a delta-sigma modulator are disclosed. The output of the mismatch noise shaper is fed back to the summer as a feedback signal that is responsive to the mismatch noise shaper. At appropriate times, the mismatch noise shaper selectively overrides the quantizer so that the output of the noise shaper differs from an output of the quantizer. The overriding feature distinguishes the present invention from a DEM, as the output of a DEM is only a re-ordering of the same number of elements as its input. The mismatch noise shaper selectively overrides the quantizer when the output of the quantizer has prevented the mismatch noise shaper to control selection of elements at the output of the mismatch noise shaper for a pre-determined time period.

Description

BACKGROUND OF THE INVENTION

FIELD OF THE INVENTION

The The present invention generally relates to delta-sigma modulators and especially mismatch noise shapers, integrated into the main loops of the delta-sigma modulators are.

BACKGROUND OF THE INVENTION

Delta-sigma modulators are in digital-to-analog converters ("DACs") and analog-to-digital converters ("ADCs") are particularly useful. The delta-sigma modulator uses oversampling to quantize noise power over the oversampling frequency band which is typically much larger than the input signal bandwidth. Furthermore leads the Delta sigma modulator undergoes noise shaping by acting as a high pass filter for noise acts. Most of the quantization noise performance is thereby pushed out of the signal band.

Of the typical delta-sigma modulator in an ADC includes an input summer, which sums the analog input signal with a negative feedback, an analog linear (loop) filter, a quantizer and a feedback loop with a digital-to-analog converter unit (Feedback DAC unit) the quantizer output and the inverting input of the input summer coupled. A delta-sigma DAC is similar to the ADC. A delta-sigma DAC has a digital input summer, a digital linear Filter, a digital feedback loop, a quantizer and an output DAC unit at the modulator output on. In the first-order modulator, the linear filter comprises a single integrator stage; the filter in higher-order modulators usually includes a cascade of a corresponding number of Integrator stages. Higher modulators Ordering has improved quantization noise transfer characteristics over modulators lower order, but stability becomes a more critical design factor, though the order increases. For Given a given topology, the quantizer may be either a one-bit quantizer or a multi-bit quantizer.

The Feedback DAC unit for multi-bit delta-sigma ADCs and the output DAC unit for a multi-bit delta-sigma DAC are typically weighted conversion elements (e.g. different DAC elements for a DAC unit). Each transformation element (eg DAC element) Converts a digital bit to an analog voltage or analog Current with weighted step around. The currents or voltages passing through generates the weighted conversion elements for the digital word The converted is then summed to the analog To produce output signal. A mismatch between conversion elements however, that causes the weighted steps of the stream or the voltage deviate from their ideal values of the weighted steps. The deviations can a result of differences being among the transformation elements exist through the manufacturing or manufacturing processes. Element mismatches are the result of mismatch noise and distortion in the output signal. As a result, there is usually a dynamic element matching circuit (DEM) at the entrances of the Conversion elements (eg DAC elements) and the DEM circuit distributes the mismatch noise over the analog output band.

Various well-known DEM structures exist. Exemplary DEM structures include cylinder shifting, averaging individual levels, butterfly steering and weighted data averaging. However, DEM circuits have significant disadvantages on. In multi-bit modulators, for example, the DEM circuit relatively large, especially in ADCs with high voltage, which has a large manufacturing geometry require. In the case of a delta sigma DAC, the DEM circuit can often become tonal, whereby sound noise is added to the output signal. In addition, there is a tendency that the DEM circuit becomes tonal because the DEM circuit is typical is a low-order delta-sigma modulator.

A DEM circuit is typically located outside the main loop of a Delta sigma modulator because of mismatch noise from the feedback loop generally not affected and not shaped. consequently In general, the DEM circuit is characterized by the output signal of the Controlled quantizer. However, if the quantizer is an output signal supplies that does not allow that the DEM circuit allows the use of DAC elements for a period of time so variable controls and selects that they have certain values, then the operation of the DEM circuit actually reduced to reducing mismatch noise.

In US Pat. No. 6,346,898 B1 For example, a multilevel analog-to-digital data converter using delta-sigma modulation is disclosed. An analog input signal is summed in a summer with an analog feedback signal provided by a DAC array in the feedback loop. The signal from the summer becomes a Noise shaping filter and fed from there as an analog signal to the multilevel quantizer with a dynamic element matching (DEM) circuit. The output of the multilevel quantizer is provided to a digital filter and is also provided as an input to the DAC array. The DEM receives the multi-bit output of the multilevel quantizer and outputs switching control signals to a switching unit. In the switching section, different voltages are switched by a voltage divider selectably to one of the inputs of comparators. The comparators receive at their second input the analog signal from the noise shaping filter. The DEM switch control is integrated in the multilevel quantizer in a separate feedback arrangement. The DEM switching control changes the behavior of the quantizer depending on the output signal. The function of the DEM switch control is to avoid the output of a constant multi-bit signal when the analog input signal is constant for a predetermined time. This reduces the reduction in digital noise while maintaining high speed operation.

US 2002/0057214 A1 suggests a delta-sigma data converter which transforms an analog input signal into a digital output signal. It is also an object to reduce the quantization or digitization error. The reduction of the quantization error in a constant signal is accomplished by adding or convolving a noise signal (thermometer code signal) to the output of the quantizer using a pseudo-random generation digital dithering module, see, for example, Paragraph. This means that the digital output is the quantized signal of the quantizer superimposed with a noise or dither signal.

A similar arrangement is made by US Pat. No. 6,344,812 B1 in which a thermometer signal is also processed to approximate a pseudorandom number or a noise signal added to the quantized signal.

The The present invention recognizes the desire for one and the need for one Circuit (eg similar a DEM circuit, the mismatch noise forms) to the output of the quantizer oversteer, as appropriate and / or required. In particular, the present recognizes Invention this desire and need when the quantizer produces an output signal supplies that does not allow that the DEM circuit allows the use of DAC elements for a period of time so variable controls and selects that they have certain values. The present invention eliminates the problems and disadvantages encountered in the prior art were.

SUMMARY OF THE INVENTION

The Invention is in the claims 1, 4, 6 and 7, respectively. Specific embodiments are in the dependent claims explained.

The Principles of the present invention are generally in one Mismatch noise shaper embodies integrated into the main loop of a delta-sigma modulator is.

Of the Quantizer of the delta-sigma modulator delivers at least three Quantization levels and the mismatch noise shaper designed the use of mismatched elements for the three or more quantization levels. The output of the mismatch noise shaper becomes the summer as a feedback signal attributed to that the mismatch noise shaper responds. To suitable Times overdriven the mismatch noise shaper selectively the quantizer, so that the output signal of the noise shaper differs from an output signal of the quantizer. The override feature distinguishes the present invention from a DEM, since the output signal a DEM just a rearrangement of the same number of elements as their input signal is. The mismatch noise shaper overdrives the quantizer selectively when the output of the quantizer for one predetermined period has prevented the mismatch noise shaper the selection of elements at the output of the mismatch noise shaper controls.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding The present invention and its advantages will now be apparent the following descriptions in conjunction with the accompanying drawings Reference is made, in which:

1 FIG. 12 is a block diagram of an exemplary delta-sigma modulator having a mismatch noise shaper integrated with the main loop according to the present invention; FIG.

2 FIG. 12 is a table of input and output values for an exemplary two-element mismatch noise shaper according to the present invention; FIG.

3A Fig. 10 is a block diagram of an exemplary mismatch noise shaper showing the main operating components according to the present invention;

3B FIG. 10 is an exemplary pseudocode algorithm provided by the exemplary mismatch noise shaper of FIG 3A implemented and executed according to the present invention;

4 Fig. 10 is a block diagram of an exemplary analog-to-digital converter ("ADC") embodying the mismatch noise shaper in the main loop of the delta-sigma modulator according to the present invention;

5 Figure 10 is a block diagram of an exemplary digital-to-analog converter ("DAC") that embodies the mismatch noise shaper in the main loop of the delta-sigma modulator according to the present invention; and

6 Figure 10 is a block diagram of an exemplary mismatch noise shaper according to the present invention, wherein the mismatch noise shaper has multiple stages.

DETAILED DESCRIPTION OF THE INVENTION

The principles of the present invention and their advantages are best understood by reference to the illustrated embodiment (s) which are incorporated herein by reference 1 to 6 of the drawings, in which like numerals denote like parts.

With reference now to 1 FIG. 10 is a block diagram of an exemplary delta-sigma modulator. FIG 100 with a mismatch noise shaper 108 , which is integrated into the main loop, shown according to the present invention. The delta-sigma modulator 100 has a summer 102 , a loop filter 104 , a quantizer 106 and a mismatch noise shaper 108 which are coupled in series, as in 1 shown. The summer 102 receives as its input signals an input signal 101 and a feedback signal that is an output signal 109 from the mismatch shaping device 108 is. The summer 102 determines a difference or error signal 103 between the input signal 101 and the output signal 109 and spend this.

The loop filter 104 receives the difference or error signal 103 from the output of the summer 102 , The loop filter 104 filters the difference or error signal 103 and gives the filtered signal to the quantizer 106 out. The quantizer 106 digitizes the filtered signal and provides a digital output signal 107 to the mismatch noise shaper 108 , The mismatch noise shaper 108 receives as its input the digital output signal 107 from the quantizer 106 , The mismatch noise shaper 108 thus provides the output signal 109 , As previously stated, the output signal becomes 109 from the mismatch noise shaper 108 to the summer 102 recycled. The output signal 109 will also work in a digital-to-analog converter ("DAC") unit 110 fed. The DAC unit 110 owns different DAC elements 112A . 112B . 112C , ... 112N , The output signal 109 provides an output to the DAC unit 110 which in turn determines and controls how the DAC elements 112A . 112B . 112C , ... 112N to be used and which respective bit values of each of the DAC elements 112A . 112B . 112C , ... 112N to be assigned.

With reference now to 2 is a table 200 of input and output values for an exemplary two-element mismatch noise shaper 108 (For example, the quantizer has three quantization levels and the mismatch noise shaper 108 illustrates the use of mismatched elements for the three quantization levels) according to the present invention. For this example, the delta-sigma modulator would 100 from 1 a DAC unit 110 with only two DAC elements 112A and 112B exhibit. The mismatch noise shaper 108 would still be the output from the quantizer 106 receive. The mismatch noise shaper 108 would also have a value for the DAC element 112A (eg element 1) and another value for the DAC element 112B (eg element 2).

If in table 200 the input signal 107 the mismatch noise shaper 108 Zero (0), then the output signal 109 the mismatch noise shaper 108 Zero (0) for the element 1 and zero (0) for the element 2. In this case, the mismatch noise shaper 108 do not control the usage and bit values for elements 1 and 2, since both of their values must be zero (0). When the input signal 107 the mismatch noise shaper 108 Two (2) is, then the output is as well 109 the mismatch noise shaper 108 One (1) for the element 1 and one (1) for the element 2. In this similar situation, the mismatch noise shaper also can not form the mismatch noise and use the and bit values for elements 1 and 2, since both of their values must be one (1).

In an exemplary two-element mismatch noise shaper 108 is the only scenario that exists in which the mismatch noise shaper 108 can mismatch noise when the input signal 107 is equal to one (1). In this case, either the output signal 109 One (1) for element 1 and zero (0) for element 0 or zero (0) for element 1 and one (1) for element 1. The mismatch noise shaper 108 then makes a decision as to which element has which value.

If, however, the output signal 109 maintains a value of either zero (0) or two (2) for a period of time, then the effect of the mismatch noise shaper becomes 108 canceled. The mismatch noise shaper 108 can not make a decision for a period of time and can not control the selection of and the values for the mismatch noise shaping elements when the output signal 109 either zero (0) or two (2). Consequently, the operation of the mismatch noise shaper becomes 108 actually canceled. To eliminate this negative effect, the mismatch noise shaper overrides 108 the output of the quantizer 106 (eg input signal 107 the mismatch shaping device 108 ), so that the output signal of the mismatching device 108 from the output of the quantizer 106 different. The mismatch noise shaper 108 overrides the quantizer 106 when the output signal of the quantizer 106 for a predetermined period of time has prevented the output of the mismatch noise shaper 108 controls the selection and values for the elements.

With reference now to 3A FIG. 12 is a block diagram of an exemplary mismatch noise shaper. FIG 108 showing the main operating components shown and explained in accordance with the present invention. The high level block diagram shows the mismatch noise shaper 108 with an arithmetic unit ("ALU") 302 , a storage system 304 and a comparator logic 306 which are coupled in series with each other. The output signal of the ALU 302 gets into the input of the storage system 306 fed and the output signal of the storage system 304 will turn into the input of the comparator logic 306 fed. The comparator logic 306 also receives the output signal 107 as another input signal. The comparator logic 306 also provides the output signal 109 , The output signal of the storage system 304 will be to another input of the ALU 302 returned and the output signal 109 the comparator logic 306 becomes also another entrance of the ALU 302 recycled.

The storage system 304 can change the current value of the input signal 107 receive and save. The storage system 304 can also store a counter that tracks different time cycles. The counter starts when a value of the input signal 107 is received for the first time, and the counter is reset when the value of the input signal 107 or if the mismatch noise shaper 108 the quantizer 106 overdriven. Thus, an implementation for the mismatch noise shaper includes 108 the comparator logic 306 which determines, using the counter, whether the input signal 107 has maintained a specific value for a predetermined period of time.

Another implementation involves the use of a state variable (s). The comparator logic 306 may be a value (values) for the state variable (s) of the mismatch noise shaper 108 determine. The state variable (s) has a value (s) having (a) certain limit (s) so that when it is reached, the mismatch noise shaper 108 selectively the quantizer 106 overdriven. The specific limit is due to the output of the quantizer 106 defined (eg input signal 107 into the mismatch noise shaper 108 ) that continuously maintains one or more values that prevent the mismatch noise shaper for the predetermined period of time 108 the selection of elements (eg the DAC elements 112A . 112B . 112C , ... 112N ) controls. Therefore, decisions of the delta-sigma modulator 100 from 1 by the mismatch noise shaper 108 that the quantizer 106 overdriven, slightly degraded to the operation of the mismatch noise shaper 108 to improve. In other words, the noise shaping operation by the delta-sigma modulator 100 over the quantizer 106 may in exchange for better performance of the mismatch noise shaper 108 a bit abandoned.

With reference now to 3B is an exemplary pseudocode algorithm 340 provided by the exemplary mismatch noise shaper 108 from 3A implemented and executed in accordance with the present invention. Exemplary state variables for the mismatch noise shaper 108 are defined as I1 and I2. State variables I1 and I2 may be integral state variables generated by the integrators of the mismatch noise shaper 108 to be delivered. For example, I1 and I2 represent the first and second integrals of using elements 1 and 2. The mismatch noise shaper 108 reforms the mismatch noise to the second order by controlling both integrals to zero. A second order modulator is preferred for mismatch noise shaping because a first order modulator system is usually insufficient and often tonal. Typically, higher order mismatch shaping modulators are difficult to implement because of stability issues. The methods disclosed by the present invention enable higher order modulators to be realistically implemented without stability problems. The state variables I1 and I2 are in the memory system 304 saved. In the pseudocode algorithm 340 E1 represents element 1 and E2 represents element 2 representing elements 1 and 2 in table 200 of FIG 2 are. The values for the input signal 107 and E1 and E2 of the output signal 109 , such as For example, example values in table 200 of FIG 2 can be detected by the mismatch noise shaper 108 by hard-wiring the values in the comparator logic 306 to be provided. FB represents the feedback value of both E1 and E2 summed up by the comparator logic 306 into the ALU 302 is returned. "MS_in" represents the value of the input signal 107 for the mismatch noise shaper 108 represents.

The pseudocode algorithm 340 starts with the code part 350 , The code part 350 reflects a condition under which the comparator logic 306 determines whether one of the certain limits (eg an upper limit) of the state variable has been reached. In this example, the upper limit condition is represented by I1> 0 and I2> 3. If such a condition occurs, the comparator logic overrides 306 the output of the quantizer 106 and sets E1 = 1 and E2 = 0 for the output signal 109 , The pseudocode algorithm 340 next goes to the code part 352 , The code part 352 represents a situation in which the comparator logic 306 determines if another of the certain limits (eg, a lower limit) of the state variable has been reached. In this example, the condition of the lower bound is identified by if I1 <0 and I2 <-3. When such a lower limit has been reached, the comparator logic overrides 306 the output of the quantizer 106 and sets E1 = 0 and E2 = 1 for the output signal 109 ,

If a certain limit (eg, either the upper or lower limit) has not been reached, then the pseudocode algorithm goes 340 to the code part 354 further. The code part 354 provides the comparator logic 306 which determines that a certain limit (eg, either the upper or lower limit) has not been reached and the comparator logic 306 overrides the output signal of the quantizer 106 Not. In this case, the comparator logic leads 306 the pseudocode algorithm 340 according to typical operations and a mismatch noise shaping operation for the delta-sigma modulator 100 out. In particular, the code part reflects 354 the comparator logic 306 which determines if MS_in = 1. If so, then the comparator logic applies 306 Decisions to shape the mismatch noise for the delta-sigma modulator 100 according to a typical mismatch noise shaping operation. The code part 354 represents that if MS_in = 1 and I1 = 0 and I2> 0, then the comparator logic 306 the mismatch noise forms by taking E1 = 1 and E2 = 0 for the output signal 109 puts. Otherwise, the comparator logic sets 306 E1 = 0 and E2 = 1 for the output signal 109 in shaping the mismatch noise.

On the other hand, if the comparator logic 306 determines that MS_in is not equal to 1 (eg equal to 0 or 2), then E1 is set equal to E2, which is set equal to MS_in divided by 2. In this scenario, the comparator logic distracts 306 simply the value of the output signal 109 the mismatch noise shaper 108 so that it simply matches the value of the output signal (eg input signal 107 ) of the quantizer 106 follows.

The pseudocode algorithm 340 then goes to the code part 356 , The code part 356 reflects the update of the state variables that the ALU 302 performs. The ALU 302 updates the state variables by setting the new value of I1 equal to the value of E1 subtracted from the sum of the old value of I1 and the current value of E2. The ALU 302 also sets the new value of I2 equal to the old value of I2 and the new value of I1. The ALU 302 also calculates the new value of FB by summing up the current values of E1 and E2, as summarized by the ALU 302 from the comparator logic 306 be received.

With reference now to 4 FIG. 4 is a block diagram of an exemplary analog-to-digital converter ("ADC"). 400 , the mismatch noise shaper 108 in the main loop of a delta-sigma modulator for the ADC 400 embodied in accordance with the present invention. The delta-sigma modulator comprises a summer 102 , an analog loop filter 404 as a loop filter 104 , an N + 1-level quantizer 406 (where N is greater than 1) as a quantizer 106 , a mismatch noise shaper 108 which are coupled in series, as in 4 ge shows. An internal N-element DAC unit 410 is also in a feedback loop between the output 109 the mismatch noise shaper 108 and the summer 102 coupled. DAC elements are part of the internal N-element DAC unit 410 , An analog loop filter 401 is in the line with the input signal 101 of the summer 102 coupled. The summer 102 gives a difference or error signal 103 off, which is the difference between the input signal 101 and the feedback output from the N-bit internal DAC unit 410 is. A digital decimation filter 412 is with the exit 109 the mismatch noise shaper 108 coupled to a digital output value 414 to be delivered by the ADC 400 from the input signal 101 is converted.

With reference now to 5 FIG. 4 is a block diagram of an exemplary digital-to-analog converter ("DAC"). 500 , the mismatch noise shaper 108 in the main loop of a delta-sigma modulator for the DAC 500 embodied in accordance with the present invention. The delta-sigma modulator comprises a summer 102 , a digital loop filter 504 as a loop filter 104 , an N + 1-level cancellation quantizer 506 (where N is greater than 1) as a quantizer 106 , a mismatch noise shaper 108 which are coupled in series, as in 5 shown. The output signal 109 the mismatch noise shaper 108 becomes the summer 102 recycled. A digital interpolation filter 501 is in the line with the input signal 101 coupled. The summer 102 receives the input signal 101 and further receives the output signal 109 from the mismatch noise shaper 108 containing the feedback signal from the internal N-element DAC unit 510 is. The summer 102 gives a difference or error signal 103 off, which is the difference between the input signal 101 and the output signal 109 is. An internal DAC unit 510 is also for receiving the output signal 109 the mismatch noise shaper 108 coupled. The DAC elements are part of the internal N-element DAC unit 510 , An analog low-pass filter 512 is to the output of the internal N-bit DAC unit 510 coupled and removes noise outside the band. The analog low-pass filter provides an analog output signal 514 that through the DAC 500 from the input signal 101 is converted.

With reference now to 6 FIG. 10 is a block diagram of an exemplary mismatch noise shaper. FIG 108 shown with multiple stages according to the present invention. 6 shows that the exemplary mismatch noise shaper 108 several stages 602 . 604 . 606 . 608 . 610 . 612 and 614 having. One of the early stage outputs 602 gets into the stage 604 fed and another of its output signals is in the stage 606 fed. One of the output signals of the stage 604 will turn into the stage 608 fed and another output signal is in the stage 610 fed. Further, one of the output signals of the stage 606 in the stage 612 fed and another output signal is in the stage 614 fed. The steps 608 . 610 . 612 and 614 each have two output signals, and these stages provide a total of eight output signals for eight respective elements (eg, eight DAC elements).

The exemplary mismatch noise shaper 108 also provides for a return from the later stages to the earlier stages. The steps 608 and 610 see, for example, a return to the level 604 before and the steps 612 and 614 see a return to the stage 606 in front. The steps 604 and 606 also see a return to the stage 602 in front. The feedback provides information on previous stages to determine, depending on the states of the stages, or indicate whether the output of the quantizer 106 should be overridden. The mismatch noise shaper 108 can be configured to use earlier stages (such as the levels 602 . 604 and 606 ) Make decisions based on the states of later stages (eg the levels 608 . 610 . 612 and 614 ).

The The present invention provides a method and system for integration a mismatch noise shaper into the main loop of a delta-sigma modulator ready. The present invention carries the output of the mismatch noise shaper to the summer of the delta-sigma modulator back. The present invention enables that the mismatch noise shaper selectively selects the quantizer overloaded at appropriate times, such that the output signal of the noise shaping device of differs an output signal of the quantizer. The present Invention allows that the mismatch noise shaper selectively overrides the quantizer, if the output of the quantizer for a predetermined period of time has prevented the mismatch noise shaper the selection of elements at the output of the mismatch noise shaper controls.

Although the invention has been described with reference to specific embodiment (s), these descriptions are not intended to be limiting. Various modifications of the disclosed embodiments as well as alterna Exemplary embodiments of the invention will be apparent to those skilled in the art upon reference to the description of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention.

Claims (7)

Delta-sigma modulator ( 100 ) with: a summer ( 102 ), which is designed to receive both an input signal ( 101 ) as well as a feedback signal ( 109 ) and receive a difference signal ( 103 ) to determine a loop filter ( 104 ), which is designed to receive the difference signal ( 103 ), a multi-bit quantizer ( 106 ) which is adapted to quantize the filtered signal and a mismatch noise shaper ( 108 ) designed to reduce the use of elements at an output of the delta-sigma modulator ( 100 ) to adapt; where the summer ( 102 ), the loop filter ( 104 ), the quantizer ( 106 ) and the mismatch noise shaping device ( 108 ), the feedback signal ( 109 ) to the mismatch noise shaper ( 108 ) reacts; and wherein the mismatch noise shaping device ( 108 ) with the quantizer ( 106 ) and a digital output signal ( 107 ) receives from the quantizer, characterized in that the mismatch noise shaping device ( 108 ) the feedback signal ( 109 ) outputs; wherein the mismatch noise shaping device ( 108 ) a counter ( 304 ), which is adapted to count up to a predetermined period of time, when the digital output signal ( 107 ) is held at a specific value for the predetermined period, and when the counter has counted until the predetermined time, the mismatch noise shaper ( 108 ) is adapted to the quantizer ( 106 ) selectively override; or wherein the mismatch noise shaping device ( 108 ) a comparator logic ( 306 ) configured to determine a state variable (I1, I2) of the mismatch noise shaper, the mismatch noise shaper configured to selectively control the quantizer (12). 106 ), when the state variable has reached a certain limit and the particular limit is defined by the output of the quantizer, which continuously maintains one or more variables for a predetermined period of time, which prevents the mismatch noise shaper from controlling the selection of the matching elements. A delta-sigma modulator according to claim 1, wherein said mismatch noise shaping means ( 108 ) several stages ( 602 - 614 ) connected in series, the first stage ( 602 ) the digital output signal ( 107 ) and the last stage ( 608 - 614 ) the feedback signal ( 109 ) and a later stage ( 604 - 606 ; 608 - 614 ) is designed to return to an earlier stage ( 602 ; 604 - 606 ). A delta-sigma modulator according to claim 1, wherein said mismatch noise shaping means ( 108 ) is a second-order or higher-order delta-sigma modulator. A method of delta-sigma modulation of a signal, comprising: receiving both an input signal ( 101 ) as well as a feedback signal ( 109 ) by a summer ( 102 ) and determining a difference signal ( 103 ) by the summer ( 102 ), Filtering the difference signal ( 103 ) through a loop filter ( 104 ), Quantizing the filtered signal by a quantizer ( 106 ), and designing the use of mismatched elements by a mismatch noise shaper ( 108 ), which is a digital output signal ( 107 ) from the quantizer ( 106 ), characterized by returning an output of the mismatch noise shaper ( 108 ) as feedback signal ( 109 ) to the summer ( 102 ), so that the feedback signal ( 109 ) responds to the mismatch noise shaper; wherein the shaping by the mismatch noise shaper ( 108 ): selective override of the quantizer ( 106 ) by the mismatch noise shaping device ( 108 ), when the digital output signal ( 107 ) of the quantizer for a predetermined period has prevented the mismatch noise shaper from controlling the selection of elements at the output of the mismatch noise shaper, or selectively overriding the quantizer (Fig. 106 ) by the mismatch noise shaping device ( 108 ), when a state variable of the mismatch noise shaper has reached a certain limit as determined by the digital output signal (Fig. 107 ) of the quantizer which continuously maintains, for a predetermined period of time, one or more values which the mismatch noise shaper ( 108 ) prevents selection of the mismatching elements. The method of claim 4, wherein the mismatch noise shaper ( 108 ) several stages ( 602 - 614 ), the method further comprising influencing decisions made by previous stages ( 602 ; 604 - 606 ), by states of later stages ( 604 - 606 ; 608 - 614 ). Analog-to-digital converter ( 400 ) comprising: a delta-sigma modulator ( 100 ) according to one of claims 1 to 2, wherein the loop filter is an analog loop filter ( 404 ) and the multi-bit quantizer is an N + 1-plane quantizer ( 406 ); an internal N-element digital-to-analog converter unit ( 410 ) with a number N of DAC elements, the digital-analog unit ( 410 ) in a feedback loop between the output of the mismatch noise shaper ( 108 ) and the summer ( 102 ) is coupled; another analog loop filter ( 401 ), which is in a line with the input signal ( 101 ) of the summer ( 102 ) is coupled; and a digital decimation filter ( 412 ) connected to the output of the mismatch noise shaper ( 108 ) and is adapted to receive the feedback signal ( 109 ) and a digital output value ( 414 ) to deliver. Digital-to-analog converter ( 500 comprising: a delta-sigma modulator according to any one of claims 1 to 2, wherein the loop filter comprises a digital loop filter ( 504 ) and the quantizer is an N + 1-level quantizer ( 506 ); an internal N-element digital-to-analog converter unit ( 510 ) with a number N of DAC elements, the digital-analog unit ( 510 ) with the output of the mismatch noise shaper ( 108 ) and is adapted to receive the feedback signal ( 109 ) to recieve; a digital interpolation filter ( 501 ) connected to a line with the input signal of the summer ( 102 ) is coupled; and an analog loop filter ( 512 ) connected to an output of the N-element digital-analog unit ( 510 ) is coupled.