CN111010184B - High-order multi-bit continuous time sigma delta modulator and method for improving DAC mismatch thereof - Google Patents

Abstract

The invention provides a high-order multi-bit continuous time sigma delta modulator and a method for improving the mismatch of a DAC (digital-to-analog converter), wherein the method is matched with a quantizer and a feedback DAC of the modulator, so that the complexity of operation can be reduced to a certain extent, and the circuit area and the power consumption can be saved. The modulator comprises a digital integrator, a quantizer, a DEM module, a decoding unit and a plurality of feedback DACs. The circuit modules related to DAC mismatch improvement are a quantizer, a DEM module and a feedback DAC. According to the method, a high-speed high-precision comparator is used for outputting a thermometer code, the thermometer code is scrambled by a DEM module, and an output result is latched and output to a current rudder type feedback DAC by a latch, so that different DAC conduction units can be selected under the same comparison result, and the improvement of DAC nonlinear distortion is realized.

Description

High-order multi-bit continuous time sigma delta modulator and method for improving DAC mismatch thereof

Technical Field

The invention belongs to the technical field of wireless communication receiver systems, and particularly relates to a high-order multi-bit continuous-time sigma delta modulator and a method for improving feedback DAC mismatch thereof.

Background

The front end of the radio frequency receiving circuit amplifies and down-converts the signal received from the antenna to an Analog baseband, and then an Analog-to-Digital Converter (ADC) converts the Analog baseband signal to a digital baseband signal so as to facilitate the subsequent operations of demodulating and decoding the signal by the digital baseband circuit. The sigma delta ADC is distinguished by its self-contained anti-aliasing properties and outstanding performance in terms of bandwidth and power consumption, and is the most popular analog-to-digital converter used in the field of wireless communication receivers. The most critical modules in the ΣΔ ADC are two, namely a modulator and a decimation filter, wherein the modulator performs the functions of oversampling, quantization, noise shaping, etc., and the decimation filter performs the decimating of the quantized digital signal. The ΣΔ modulator is generally composed of a loop filter, a quantizer and a feedback DAC, respectively, and the error generated by the quantizer is called quantization noise, which can be shaped by a noise transfer function, and nonlinear distortion caused by mismatch between DAC units due to deviation of a manufacturing process will seriously affect the performance of the ADC as a whole, so that elimination of DAC mismatch becomes an unavoidable loop in modulator design.

Methods for improving the mismatch of the DAC are various, and can be classified into two types of calibration and shaping according to different mismatch error processing modes. The calibration can be divided into wafer factory calibration and circuit calibration, and the wafer factory calibration, as the name implies, is to calibrate the produced wafer more accurately by means of laser and the like after the production of the wafer factory, and the defect is that the influence of aging and packaging on mismatch cannot be considered; circuit calibration is to deal with mismatch by adding compensation circuits, which has the disadvantage that mismatch values need to be obtained accurately and the process can no longer handle drift better. The design thought of the sigma delta modulator is used for improving the mismatch of the DAC by means of shaping, and the mismatch of the DAC is improved by making a decision in the next clock period opposite to the previous clock period. For zero-order shaping, namely, through randomizing the input signal, the selection of different units of the DAC is realized, and the mode can effectively reduce harmonic waves, but can improve noise floor; the first-order shaping is applied more at present, and the basic principle is that the logic unit is used for regularized processing of the input signals, so that the output values can be different under the condition of the same input, the selection of different units of the DAC is realized, and the first-order shaping of the process mismatch error is achieved; higher order shaping can better handle mismatch errors, but the required hardware resources will increase substantially.

For a continuous-time ΣΔ modulator applied in the wireless communication field, the large bandwidth requirement of the application scene makes the modulator very sensitive to any increased delay, the existence of the delay may increase the order of the modulator, overload phenomenon is generated under the condition of the same input, so that the modulator cannot work, and the stability of a loop is greatly reduced under the interference of the delay. In addition, the increase in hardware resources causes a surge in power consumption and area, which adversely affects the overall system.

In summary, the elimination of DAC mismatch is an unavoidable loop in the design of the continuous-time ΣΔ modulator, but the added DEM module needs to consider the overhead of hardware resources, and needs to avoid the power consumption and the large-scale area improvement as much as possible; on the other hand, the restriction of the DEM module on the system speed needs to be considered, so that the problem of loop stability is avoided.

Disclosure of Invention

The technical solution of the present invention is to provide a high-order multi-bit continuous-time sigma delta modulator and a method for improving DAC mismatch thereof, aiming at the existing defects of the method for improving DAC mismatch applied in the continuous-time sigma delta modulator.

The technical scheme adopted for solving the technical problems comprises the following steps: a high-order multi-bit continuous time sigma delta modulator, comprising an integrator, a quantizer, a DEM module, a feedback DAC and a decoding unit; the output end of the last-stage integrator is connected with the input end of the quantizer, the output end of the quantizer is connected with the input end of the DEM module and the input end of the decoding unit, the output end of the DEM module is connected with the input end of the feedback DAC, and the output end of the feedback DAC is connected with the input end of each-stage integrator and the input end of the quantizer.

The quantizer comprises a plurality of comparators, each comparator receives a reference voltage value and a quantizer input value, and compares the reference voltage value with the quantizer input value to generate an output, wherein the reference voltage value is obtained through resistor voltage division, and the generated output forms a group of thermometer code control codes.

The DEM module comprises a plurality of stages of processing units and latches, each stage of processing unit comprises a plurality of subunits, each subunit comprises a two-input exclusive-OR gate, a D trigger and three two-input data selectors MUX 1-3 with control ends, the input of the two-input exclusive-OR gate is a comparator or the two bits Z0 and Z1 of the control code output by the former stage of processing unit, the output is used as the output result of the control code A1 to control the two-input data selectors MUX1, and the input of the two-input data selectors MUX1 is the output Q and Q of the D trigger

When A1 is 0, the output of the two-input data selector MUX1 is Q, and when A1 is 1, the output of the two-input data selector MUX1 is +.>

The output end of the two-input data selector MUX1 is connected with the input end of the D trigger; the clock signal of the D trigger is CLK1, and the output Q of the D trigger is equal to/>

The outputs of the two-input data selectors MUX2 and MUX3 are controlled as control signals in addition to the input terminal connected to MUX 1; inputs of the two-input data selectors MUX2 and MUX3 are two bits Z0 and Z1, Q and +.>

Controlling the outputs of the MUX2 and the MUX3, wherein when Q is 1, the output of the MUX2 is Z1, the output of the MUX3 is Z0, when Q is 0, the output of the MUX2 is Z0, the output of the MUX3 is Z1, and the output results of the MUX2 and the MUX3 are processed as input signals of a next stage processing subunit; the control code processed by the DEM module digital processing unit is sent into a latch, the phase difference between a clock signal CLK2 and a clock signal CLK1 of the latch is 180 degrees, when the rising edge of the CLK1 arrives, the control code is processed in the DEM processing unit, and when the rising edge of the CLK2 arrives, the processed control code is latched and output in the latch; the two clock signals CLK1 and CLK2 cause the DEM module to introduce a fixed half-clock delay that is compensated by adding a feedback DAC connected to the quantizer input.

The feedback DAC selects a current rudder configuration.

The method for improving the DAC mismatch of the high-order multi-bit continuous-time sigma delta modulator comprises the following steps:

s1, supplying power to a circuit, and obtaining reference voltage values required to be set by a plurality of comparators through resistor voltage division;

s2, respectively sending the input of the quantizer into a comparator, comparing the input with a reference voltage value one by one, and outputting the result through the comparator to obtain a group of thermometer code control codes;

s3, when the rising edge of the clock CLK1 comes, the thermometer code control code is sent into the DEM module to be processed by the digital processing unit;

s4, when the rising edge of the clock CLK2 comes, the control code processed by the DEM module is sent into the latch to latch and output, and the conducting unit of the feedback DAC is selected.

Compared with the prior art, the invention has the advantages that:

aiming at the problem of continuous-time DAC mismatch, the invention carries out scrambling processing on the thermometer code control code output by the comparator and the current rudder DAC with proper partner and adds the DEM module, and simultaneously introduces fixed delay to relax the speed requirements on the quantizer and the DEM module, thereby saving the circuit power consumption and the area and ensuring the loop stability while better improving the continuous-time sigma delta modulator DAC mismatch error.

Drawings

FIG. 1 is a schematic diagram of a ΣΔ ADC architecture according to the present invention;

FIG. 2 is a schematic diagram of a Sigma-Delta modulator architecture according to the present invention;

FIG. 3 is a schematic diagram of a circuit configuration for improving DAC mismatch according to the present invention;

FIG. 4 is a schematic diagram of the internal structure of a DEM module subunit of the present invention;

FIG. 5 is a schematic diagram of a timing relationship of sub-units of the DEM module according to the present invention;

fig. 6 is a timing diagram of DEM module output when the comparator outputs "0001" according to the invention.

Detailed Description

The invention will be further described with reference to the accompanying drawings.

The present invention provides a high order multi-bit continuous time ΣΔ modulator comprising: the digital integrator, the quantizer, the DEM module, the feedback DACs and the decoding unit.

The output end of the quantizer is connected with the input end of the DEM module and the input end of the decoding unit, the output end of the DEM module is connected with the input end of the feedback DAC, and the output end of the feedback DAC is connected with the input end of each stage of integrator and the input end of the quantizer. The improved DAC mismatch involves a circuit that primarily includes a quantizer, DEM module, and feedback DAC.

The quantizer is composed of a plurality of high-speed high-precision comparators, each comparator receives a reference voltage value and an input value of the quantizer and compares the reference voltage value with the input value of the quantizer to generate an output, wherein the reference voltage value is obtained through resistor voltage division, and the generated output forms a group of thermometer code control codes.

The DEM module consists of a plurality of stages of processing units and latches, each stage of processing unit comprises a plurality of subunits, each subunit consists of two-input exclusive-OR gates, a D trigger and three two-input data selectors MUX 1-3 with control ends, the inputs of the two-input exclusive-OR gates are two bits Z0 and Z1 of a control code output by a comparator or a previous stage of processing unit, the output is used as an output result of the control code A1 for controlling the MUX1, and the input of the MUX1 is the output Q and the output Q of the D trigger

When A1 is 0, the output of MUX1 is Q, when A1 is 1, the output of MUX1 is +.>

The output end of the MUX1 is connected with the input end of the D trigger; the clock signal of the D trigger is CLK1, and the outputs Q and +.>

The output of the MUX2 and the MUX3 is controlled by the control signal besides the input end of the MUX 1; the input of MUX2 and MUX3 is the same as the input of two-input exclusive OR gate, and outputs two bits Z0 and Z1, Q and +.>

Controls MUX2&3, when Q is 1, the output of MUX2 is Z1, the output of MUX3 is Z0, when Q is 0, the output of MUX2 is Z0, the output of MUX3 is Z1, MUX2&The output result of 3 is further processed as the input signal of the next stage processing subunit. The control code after the digital processing is sent into a latch, the phase difference of a clock signal CLK2 and a clock signal CLK1 of the latch is 180 degrees, when the rising edge of the CLK1 arrives, the control code is processed in a DEM processing unit, when the rising edge of the CLK2 arrives, the processed control code is latched and output in the latch, and is sent into a DAC selection conduction unit; control code implementation processed by DEM moduleThe regularity of the on word is selected, i.e. the control code output by the latch is different when CLK2 different rising edges arrive, when the thermometer code output by the comparator is the same when CLK1 rising edge arrives. Meanwhile, under the interaction of CLK1 and CLK2, the input to the output of the control code has a fixed delay of half a clock period, the fixed delay can be compensated by adjusting the structure of the modulator, and compared with the method of simply adding the DEM module to introduce an indefinite delay, the fixed delay can reduce the requirements of the modulator on the speed of the comparator and the DEM module, so that the design difficulty is relatively reduced. Since a delay of a fixed half clock period is introduced, the delay needs to be compensated on the modulator architecture, an additional feedback DAC needs to be introduced, the input end of the additional feedback DAC is connected with the output end of the DEM module as well as other feedback DACs, the output end of the additional feedback DAC is connected with the input end of the quantizer to form a zero-order feedback loop, and the feedback DACs with the same number as the order of the modulator are respectively connected with the output end of each integrator. The feedback DAC selects a current steering structure, the current steering DAC has high precision and high speed, and the requirement of the sigma delta modulator on bandwidth can be better met.

The quantization error of the sigma delta modulator can be shaped by a noise transfer function, so the precision requirement on the quantizer is not high, and a plurality of high-speed high-precision comparators can be used for comparing input signals to generate a group of thermometer codes; thermometer codes are also necessary for processing of the DEM module; meanwhile, the thermometer codes are consistent with the selection of the conducting units of the DAC, that is to say, the current source weights of the current steering DAC are the same, and the current steering DAC arranged in the way can achieve better matching effect in the CMOS process manufacturing process. As described above, the method of the present invention has the advantage that the hardware cost is greatly increased due to the excessively high quantization bit number, and the present invention has the advantages of high speed and moderate precision, and the quantization bit number of the quantizer is generally smaller than 5 bits.

The invention provides a method for improving DAC mismatch in a continuous-time sigma delta modulator, comprising the following steps:

s1, supplying power to a circuit, and obtaining reference voltage values required to be set by a plurality of comparators through resistor voltage division;

s2, respectively sending the input of the quantizer into a comparator, comparing the input with a reference voltage value one by one, and outputting the result through the comparator to obtain a group of thermometer code control codes;

s3, when the rising edge of the clock CLK1 comes, the thermometer code control code is sent into the DEM module to be processed by the digital processing unit;

s4, when the rising edge of the clock CLK2 comes, the control code processed by the DEM module is sent into the latch to latch and output, and the conducting unit of the feedback DAC is selected.

Examples:

as shown in fig. 1, one embodiment of improving DAC mismatch in a ΣΔ modulator according to the method proposed by the present invention is shown. The following discussion of the embodiments of the invention is merely exemplary in nature, and is in no way intended to limit the invention or its applications or uses.

In this embodiment, the ΣΔ ADC is formed by an antialiasing filter 100, a ΣΔ modulator 101, a decimation filter 102, and a FIR filter 103, and the ΣΔ modulator 101 according to the present invention is formed by a first integrator 111, a second integrator 112, a quantizer 113, a dem module 114, a first feedback DAC 115, a second feedback DAC 116, a third feedback DAC 117, and a thermometer code binary code decoding circuit 118, as shown in fig. 2, wherein the circuit modules related to improving DAC mismatch include the quantizer 113, the dem module 114, the first feedback DAC 115, the second feedback DAC 116, and the third feedback DAC 117. An embodiment of the present invention will be described in detail with reference to fig. 2.

After the signals subjected to out-of-band interference filtering by the anti-aliasing filter 100 are subjected to difference with the signals outputted by the third feedback DAC 117, the signals are sent to the first integrator 111 for first-stage integration processing, the signals outputted by the first integrator 111 are subjected to difference with the signals outputted by the second feedback DAC 116, the signals outputted by the second integrator 112 are sent to the second integrator 112 for second-stage integration processing, the signals outputted by the second integrator 112 are subjected to difference with the signals outputted by the first feedback DAC 115, the signals are sent to the quantizer 113 for sampling and comparison, and the signals are transferred from an analog domain to a digital domain, in this embodiment, 4 comparators are used by the two-bit quantizer, the outputs of the two-bit quantizer are 4-bit thermometer codes, the thermometer codes are sent to the thermometer code binary code conversion decoding circuit 118 on one hand, the thermometer codes are converted into binary codes for output, and sent to the extraction filter 102 and the FIR filter 103 of the subsequent stages for down sampling, and the digital circuits for signal processing; on the other hand, the thermometer code is sent to the DEM module 114 to be scrambled and latched and output when the CLK2 clock signal arrives, and the control code processed by the DEM module 114 controls the on-off of the first feedback DAC 115, the second feedback DAC 116 and the third feedback DAC 117, selects the on-state units of the first feedback DAC 115, the second feedback DAC 116 and the third feedback DAC 117, and completes the conversion from the digital signal to the analog signal.

The circuit for improving the mismatch of the DACs mainly comprises a quantizer 113, a DEM module 114, a first feedback DAC 115, a second feedback DAC 116 and a third feedback DAC 117, and the three feedback DACs are similar in structure, a current rudder structure is selected, the current rudder DAC has high precision and high speed, and can better meet the requirement of the sigma delta modulator on bandwidth, wherein the first feedback DAC 115 is introduced to compensate loop delay introduced by the DEM module 114, so that the stability of a loop is ensured. In fig. 3, the connection between the quantizer 113, dem block 114 and the first feedback DAC 115 is illustrated in more detail, and only the most dominant input-output characteristics of each block and signal flow are preserved.

In this embodiment, the quantizer selects a two-bit structure, so that 4 comparators including a first comparator 301, a second comparator 302, a third comparator 303, and a third comparator 304 are used, each comparator receives a reference voltage value and a signal input to generate a one-bit comparison result, and outputs of the 4 comparators form a set of thermometer code control codes. The outputs of the first comparator 301 and the second comparator 302 are connected to two input ends of the first DEM subunit 311, the outputs of the third comparator 303 and the third comparator 304 are connected to two input ends of the second DEM subunit 312, the two outputs of the first DEM subunit 311 are respectively connected to the input ends of the third DEM subunit 321 and the fourth DEM subunit 322, meanwhile, the two outputs of the second DEM subunit 312 are respectively connected to the input ends of the DEM subunit 321 and the fourth DEM subunit 322, the DEM subunit works when the rising edge of CLK1 comes, the output results of the third DEM subunit 321 and the fourth DEM subunit 322 are respectively sent to the first latch 331, the second latch 332, the third latch 333 and the fourth latch 334, and latch output when the rising edge of CLK2 comes, when the output control code of the comparator is 0001, the output result of the comparator will distribute 1 control code to different output ends in different periods, and full-coverage of the feedback latch unit is realized. The output timing diagram is shown in fig. 6.

The DEM subunit is key for implementing scrambling processing on thermometer codes, and its internal structure is shown in fig. 4, and is composed of a D flip-flop 401, three two-input data selectors with control terminals, MUX 402, MUX403, MUX 404, and xor gate 405. D flip-flop 401 takes its value when the rising edge of CLK1 arrives, its output Q and

the signal of the control end of the MUX 402 is output from an exclusive OR gate 405, the input signal of the exclusive OR gate is the output control code of a comparator or the output of a processing unit at the previous stage of the DEM module, and when the output is 0, the 0 end of the MUX 402 is selected, namely, the end connected with the Q end of the D trigger; when the output is 1, the 1-terminal of MUX 402 is selected, i.e., with the +.>

One end of which is connected with the other end. The outputs Q and +.>

The control signals also control the outputs of the MUXs 403 and 404, when Q is 1, the output of the MUX 402 is Z1, the output of the MUX403 is Z0, when Q is 0, the output of the MUX 402 is Z0, the output of the MUX403 is Z1, and the output results of the MUXs 402 and 403 are processed as input signals of the next stage processing subunit.

For two input signals Z0 and Z1, which do not change over time, when Z0 and Z1 are the same, the exclusive or gate 405 outputs 0, for D flip-flop 401Q (n+1) =d (n) =q (n),the output results of muxes 403 and 404 do not change and are always the value of Z0; when Z0 is different from Z1, taking z0=0 and z1=1 as an example, the output of the exclusive or gate 405 is always 1, and there is a D flip-flop 401

The output of the D flip-flop changes when the rising edge of the CLK1 clock comes, and the output results of the muxes 403 and 404 change with the change of the Q value, when Q is 1, the output Z0 '=1=z1 of the MUX 402, and the output of the MUX403 is Z1' =0=z0; when Q is 0, the output of MUX 402 is z0 '=0=z0, and the output of MUX403 is z1' =1=z1, i.e., when the CLK1 clock rising edge arrives, the subunit performs the function of path switching for two different signals. The timing diagram is shown in fig. 5. For two input signals Z0 and Z1 changing along with time, according to the state of Z0 and Z1 when the rising edge of the CLK1 clock arrives, the output result changes along with the rising edge, and when Z0 and Z1 are the same, the output Z0 'and Z1' respectively receive the data of Z0 and Z1; when Z0 and Z1 are different, outputting data which is output when Z0 'and Z1' are not the same at the last time of Z0 and Z1 exchange.

The control code of the scrambling process is fed into latches 331, 332, 333, 334 at the arrival of the CLK1 clock rising edge, and the latches output at the arrival of the CLK2 clock rising edge. The addition of the latch eliminates burrs generated in the pre-stage scrambling process on one hand, so that the output control code is more stable; on the one hand, a delay of half a clock period is introduced and can be compensated by adding a first feedback DAC 115 to adjust the modulator structure, which fixed delay improves the loop stability while relaxing the processing speed of the comparator and DEM modules.

The invention is not described in detail in part as being well known to those skilled in the art.

Claims (4)

1. A high order multi-bit continuous time ΣΔ modulator characterized by: the digital video processing system comprises an integrator, a quantizer, a DEM module, a feedback DAC and a decoding unit; the output end of the last-stage integrator is connected with the input end of the quantizer, the output end of the quantizer is connected with the input end of the DEM module and the input end of the decoding unit, the output end of the DEM module is connected with the input end of the feedback DAC, and the output end of the feedback DAC is connected with the input end of each-stage integrator and the input end of the quantizer; the DEM module comprises a plurality of stages of processing units and latches, each stage of processing unit comprises a plurality of subunits, each subunit comprises two input exclusive-OR gates, a D trigger and three two input data selectors MUX 1-3 with control ends, the inputs of the two input exclusive-OR gates are two bits Z0 and Z1 of a control code output by a comparator or a previous stage of processing unit, the output of the two input exclusive-OR gates is used as the output result of the control code A1 to control the two input data selectors MUX1,

the input of the two-input data selector MUX1 is the output Q and the output Q of the D flip-flop

When A1 is 0, the output of the two-input data selector MUX1 is Q, and when A1 is 1, the output of the two-input data selector MUX1 is +.>

The output end of the two-input data selector MUX1 is connected with the input end of the D trigger; d (D)

The clock signal of the flip-flop is CLK1, and the output Q of the D flip-flop and

the outputs of the two-input data selectors MUX2 and MUX3 are controlled as control signals in addition to the input terminal connected to MUX 1; the inputs of the two-input data selectors MUX2 and MUX3 are the control codes output by the comparator or the previous stage processing unit

Two bits Z0 and Z1, Q and

controlling the outputs of MUX2 and MUX3, wherein when Q is 1, the output of MUX2 is Z1, the output of MUX3 is Z0, when Q is 0, the output of MUX2 is Z0, the output of MUX3 is Z1, and the output junctions of MUX2 and MUX3 are providedThe result is used as the input signal of the next stage processing subunit for processing; the control code processed by the DEM module digital processing unit is sent into a latch, the phase difference between a clock signal CLK2 and a clock signal CLK1 of the latch is 180 degrees, when the rising edge of the CLK1 arrives, the control code is processed in the DEM processing unit, and when the rising edge of the CLK2 arrives, the processed control code is latched and output in the latch; the two clock signals CLK1 and CLK2 cause the DEM module to introduce a fixed half-clock delay that is compensated by adding a feedback DAC connected to the quantizer input.

2. The high order multi-bit continuous-time ΣΔ modulator of claim 1, wherein: the quantizer comprises a plurality of comparators, each comparator receives a reference voltage value and a quantizer input value, and compares the reference voltage value with the quantizer input value to generate an output, wherein the reference voltage value is obtained through resistor voltage division, and the generated output forms a group of thermometer code control codes.

3. The high order multi-bit continuous-time ΣΔ modulator of claim 2, characterized by: the feedback DAC selects a current rudder configuration.

4. A method of improving DAC mismatch in a high order multi-bit continuous time ΣΔ modulator according to claim 3, comprising the steps of:

s1, supplying power to a circuit, and obtaining reference voltage values required to be set by a plurality of comparators through resistor voltage division;

s2, respectively sending the input of the quantizer into a comparator, comparing the input with a reference voltage value one by one, and outputting the result through the comparator to obtain a group of thermometer code control codes;

s3, when the rising edge of the clock CLK1 comes, the thermometer code control code is sent into the DEM module to be processed by the digital processing unit;

s4, when the rising edge of the clock CLK2 comes, the control code processed by the DEM module is sent into the latch to latch and output, and the conducting unit of the feedback DAC is selected.

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