DE60303566D1 - Viterbi Dekodierer für gigabit Ethernet - Google Patents

Viterbi Dekodierer für gigabit Ethernet

Info

Publication number
DE60303566D1
DE60303566D1 DE60303566T DE60303566T DE60303566D1 DE 60303566 D1 DE60303566 D1 DE 60303566D1 DE 60303566 T DE60303566 T DE 60303566T DE 60303566 T DE60303566 T DE 60303566T DE 60303566 D1 DE60303566 D1 DE 60303566D1
Authority
DE
Germany
Prior art keywords
gigabit ethernet
viterbi decoder
viterbi
gigabit
decoder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60303566T
Other languages
English (en)
Inventor
Peter J Graumann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Application granted granted Critical
Publication of DE60303566D1 publication Critical patent/DE60303566D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/6331—Error control coding in combination with equalisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0054—Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Theoretical Computer Science (AREA)
  • Artificial Intelligence (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
DE60303566T 2002-05-23 2003-05-22 Viterbi Dekodierer für gigabit Ethernet Expired - Lifetime DE60303566D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/156,292 US7139312B2 (en) 2002-05-23 2002-05-23 System and method for improving coding gain performance within gigabit phy viterbi decoder

Publications (1)

Publication Number Publication Date
DE60303566D1 true DE60303566D1 (de) 2006-04-20

Family

ID=29400593

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60303566T Expired - Lifetime DE60303566D1 (de) 2002-05-23 2003-05-22 Viterbi Dekodierer für gigabit Ethernet

Country Status (4)

Country Link
US (1) US7139312B2 (de)
EP (1) EP1365534B1 (de)
JP (1) JP2004007693A (de)
DE (1) DE60303566D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101027857B (zh) * 2004-09-29 2011-02-02 富士通株式会社 发送功率控制装置及发送功率控制方法
US7778320B2 (en) * 2005-10-03 2010-08-17 Clariphy Communications, Inc. Multi-channel equalization to compensate for impairments introduced by interleaved devices
US8139630B2 (en) * 2005-10-03 2012-03-20 Clariphy Communications, Inc. High-speed receiver architecture
US8831074B2 (en) 2005-10-03 2014-09-09 Clariphy Communications, Inc. High-speed receiver architecture
US8483343B2 (en) * 2005-10-03 2013-07-09 Clariphy Communications, Inc. High-speed receiver architecture
US8009728B2 (en) * 2005-12-09 2011-08-30 Electronics And Telecommunications Research Institute Parallel equalizer for DS-CDMA UWB system and method thereof
US8094056B2 (en) * 2006-02-02 2012-01-10 Clariphy Communications, Inc. Analog-to-digital converter
US20070183489A1 (en) * 2006-02-07 2007-08-09 Samsung Electronics Co., Ltd. Apparatus for decoding a signal and method thereof and a trellis coded modulation decoder and method thereof
US7697642B2 (en) 2006-04-17 2010-04-13 Techwell, Inc. Reducing equalizer error propagation with a low complexity soft output Viterbi decoder
US7697604B2 (en) * 2006-04-17 2010-04-13 Techwell, Inc. Dual pDFE system with forward-backward viterbi
US8938035B1 (en) 2012-02-29 2015-01-20 Marvell International Ltd. System and method for transferring data over a two-pair communication system
US9118480B2 (en) * 2013-02-11 2015-08-25 Telefonaktiebolaget Lm Ericsson (Publ) Frame quality estimation during viterbi decoding
JP5846183B2 (ja) * 2013-11-11 2016-01-20 株式会社デンソー 通信装置
US10263663B2 (en) * 2015-12-17 2019-04-16 Intel Corporation M-ary pulse amplitude modulation digital equalizer
TWI640181B (zh) * 2016-03-02 2018-11-01 晨星半導體股份有限公司 等化器裝置及使用在等化器裝置中以維特比演算法為基礎的決策方法
US11086716B2 (en) 2019-07-24 2021-08-10 Microchip Technology Inc. Memory controller and method for decoding memory devices with early hard-decode exit
US11095299B1 (en) * 2020-03-30 2021-08-17 Sitrus Technology Corporation ADC having adjustable threshold levels for PAM signal processing
US12014068B2 (en) 2021-04-27 2024-06-18 Microchip Technology Inc. System and method for double data rate (DDR) chip-kill recovery
CN117280328A (zh) 2021-06-01 2023-12-22 微芯片技术股份有限公司 存储器地址保护
WO2023055676A1 (en) 2021-09-28 2023-04-06 Microchip Technology Inc. Ldpc decoding with trapped-block management

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19545473C2 (de) 1995-12-06 1998-03-12 Kommunikations Elektronik Verfahren zur digitalen Nachrichtenübertragung über ein elektrisches Kabel
US6115436A (en) * 1997-12-31 2000-09-05 Ericsson Inc. Non-binary viterbi decoder using butterfly operations
US6108386A (en) * 1998-04-03 2000-08-22 Lucent Technologies Inc. List Viterbi algorithms for continuous data transmission
US6253345B1 (en) * 1998-11-13 2001-06-26 Broadcom Corporation System and method for trellis decoding in a multi-pair transceiver system
US6201831B1 (en) 1998-11-13 2001-03-13 Broadcom Corporation Demodulator for a multi-pair gigabit transceiver
US6378106B1 (en) * 1999-05-28 2002-04-23 Lucent Technologies Inc. Viterbi decoding using single-wrong-turn correction
JP2002050134A (ja) * 2000-05-22 2002-02-15 Fujitsu Ltd データ再生装置
TW476849B (en) * 2000-08-11 2002-02-21 Acer Labs Inc Viterbi detector for increasing the range of allowable DC drift amount

Also Published As

Publication number Publication date
JP2004007693A (ja) 2004-01-08
EP1365534A1 (de) 2003-11-26
EP1365534B1 (de) 2006-02-15
US20030219083A1 (en) 2003-11-27
US7139312B2 (en) 2006-11-21

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Legal Events

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