DE60225068T2 - NOISE REDUCTION TECHNOLOGY FOR TRANSISTORS AND SMALL ARRANGEMENTS USING EPISODIC AGITATION - Google Patents

Abstract

The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.

Description

The The present invention relates generally to transistors and small ones electronic components, including computer-readable memory devices, which can be read both statically, as with reading models for static RAMs, or dynamically, as with dynamic RAMs, where a subpoena followed by a signal development used and special method for reducing noise reading the information content of this.

In non-volatile semiconductor memories, such as EEPROMs or flash memories, the amount of data stored per memory cell has been increased to increase the storage density. At the same time, the operating voltages of such devices have been reduced to reduce power consumption. This results in a larger number of states being stored in a smaller range of voltage or current values. As the voltage or current gap between data states decreases, the effects of noise in reading those cells become more significant. For example, fluctuations in the threshold voltage value acceptable in an EEPROM cell of a 5 volt binary memory may be unacceptable for a device operating at 3 volts with four or more storable bits per cell. Some consequences of noise in a nonvolatile memory and methods of handling this are in U.S. Patent No. 6,044,019 described.

Become conventional physically larger transistors for sensitive used analog applications, whereas digital circuits in which physically small digital transistors are used in one binary Working mode, insensitive to the existing low noise level. Even non-volatile memory with four memory levels (2 bits / cell) have sufficiently large reading tolerances to, in the majority of cases across from to be generally immune to this noise. As the size of memory components but has dropped continuously, are non-macroscopic effects, for example, effects of a single electron or quantum effects, have become increasingly important, and have exacerbated the noise problem.

• [1] "Random Telegraph Noise in Deep-Submicrometer MOSFETS" von K. K. Huang, et. al., IEEE Electron Device Letters, Bd. 11, Nr. 2, Februar 1990;
• [2] "Effects of Oxide traps, interface traps, and border traps an metal-oxide-semiconductor devices" von D. M. Fleetwood, et. al., J. Appl. Phys., Bd. 73, Nr. 10, 15. Mai 1993;
• [3] "Quantum Effects an the Extraction of MOS Oxide Traps by 1/f Noise Measurements" von Andrea Pacelli, et. al., IEEE Transactions an Electron Devices, Bd. 46, Nr. 5, Mai 1999, S. 1029 ff;
• [4] "In Depth Exploration of Si-SeO2 Interface Traps in MOS Transistors Using the Charge Pumping Technique" von Daniel Bauza, et. al., IEEE Transactions an Electron Devices, Bd. 44, Nr. 12, Dezember 1997, S. 2262 ff;
• [5] "Critical Discussion an Unified 1/f Noise Models for MOSFETs" von Ewout P. Vandamme, et. al., IEEE Transactions an Electron Devices, Bd. 47, Nr. 11, November 2000, S. 2146ff;
• [6] "A Solution for Current-Voltage Characteristics of Multiple Coupled Mesoscopic Tunnel Junctions", von N. Mokhlesi et al., Superlattices and Microstructures, Bd. 21, Nr. 1, S. 15–19 (1997);
• [7] "Capacitive nature of atomic-sized structures", von G. J. lafrate et al., Physical Review B, Bd. 52, Nr. 15, S. 10 733, 15. Oktober 1995-I;
• [8] "1/f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation", von I. Bloom, et al., Applied Physics Letters 58 (15) 15. April 1991;
• [9] "The decrease of "random telegraph signal" noise in metal-oxide-semiconductor field effect transistors when cycled from inversion to accumulation", von B. Dierickx, et al., Journal of Applied Physics, 71 (4), 15. Februar 1992;
• [10] "MOSFET 1/f Noise Measurement Under Switched Bias Conditions", von A. P. van der Wel, et al., IEEE Electron Device Letters, Bd. 21, Nr. 1, Januar 2000;
• [11] "Reducing MOSFET 1/f Noise and Power Consumption by Switched Biasing", von Eric A. M. Klumperink, et al., IEEE Journal of Solid-State Circuits, Bd. 35, Nr. 7, Juli 2000, wenngleich in diesen Veröffentlichungen kein spezielles praktisches Verfahren zur Reduktion von Rauschen zur Nutzung in Speichersystemen präsentiert wird.

Various aspects of the operation of such scaled-down small components are discussed in the following documents:

• [1] "Random Telegraph Noise in Deep Submicrometer MOSFETS" by KK Huang, et. al., IEEE Electron Device Letters, Vol. 11, No. 2, February 1990;
• [2] "Effects of Oxide Traps, Interface Traps, and Border Traps on Metal-Oxide-Semiconductor Devices" by DM Fleetwood, et. al., J. Appl. Phys., Vol. 73, No. 10, May 15, 1993;
• [3] "Quantum Effects on the Extraction of MOS Oxide Traps by 1 / f Noise Measurements" by Andrea Pacelli, et. al., IEEE Transactions on Electron Devices, Vol. 46, No. 5, May 1999, p. 1029 et seq;
• [4] "In Depth Exploration of Si-SeO2 Interface Traps in MOS Transistors Using the Charge Pumping Technique" by Daniel Bauza, et. al., IEEE Transactions on Electron Devices, Vol. 44, No. 12, December 1997, p. 2262 et seq;
• [5] "Critical Discussion on Unified 1 / f Noise Models for MOSFETs" by Ewout P. Vandamme, et. al., IEEE Transactions on Electron Devices, Vol. 47, No. 11, November 2000, p. 2146ff;
• [6] "A Solution for Current-Voltage Characteristics of Multiple Coupled Mesoscopic Tunnel Junctions", by N. Mokhlesi et al., Superlattices and Microstructures, Vol. 21, No. 1, pp. 15-19 (1997);
• [7] "Capacitive nature of atomic-sized structures," by GJ Lafrate et al., Physical Review B, Vol. 52, No. 15, p. 10, 733, October 15, 1995-I;
• [8] "1 / f noise reduction of metal-oxide-semiconductor transistors by cycling from inversion to accumulation", by I. Bloom, et al., Applied Physics Letters 58 (15) April 15, 1991;
• [9] "The decrease of" random telegraph signal "noise in metal oxide semiconductor field effect transistors when cycled from inversion to accumulation", by B. Dierickx, et al., Journal of Applied Physics, 71 (4), 15 February 1992;
• [10] "MOSFET 1 / f Noise Measurement Under Switched Bias Conditions", by AP van der Wel, et al., IEEE Electron Device Letters, Vol. 21, No. 1, January 2000;
• [11] "Reducing MOSFET 1 / f Noise and Power Consumption by Switched Biasing", by Eric AM Klumperink, et al., IEEE Journal of Solid-State Circuits, Vol. 35, No. 7, July 2000, albeit in these publications No special practical method for reducing noise for use in storage systems is presented.

In addition, on the International Patent Specification No. WO 01/27931 Reference is made, which describes a process in which a set of voltages is applied to a memory cell selected for a read process, including a first control gate voltage, and the current strength of the cell is read out. The control gate voltage is then increased to a second level (or "step") and the current is read again and the process is repeated. A number of conventional read intervals are taught in which the read voltages applied to a memory cell are held constant and the cell current is measured, with the control gate voltage jumping to the next level in the series between these intervals.

Although the consequences of noise can be reduced or treated by such methods as in Patent No. 6,044,019, with an error correction code (ECC) or other equivalent error handling such as in U.S. Patent No. 5,418,752 For example, methods for reducing noise that arises in the mesoscopic region between the macroscopic and microscopic regions could provide advantages for memory.

According to the invention, a method of operating a nonvolatile memory comprises applying a set of voltages (V _aper , V _per ) to a memory unit of the nonvolatile memory during an interval (t) and determining the line characteristics (I, V _BL ) of the memory unit in response to the set of voltages, wherein the set of voltages comprises a read voltage state (V _aper ) and a time varying excitation stimulus (V _per ) component different from the read voltage state.

The inventive method can be used to save the data content of a non-volatile In the method, the interval is a read interval represents the measured characteristic represents a parameter value, the with the data content of the memory unit of the memory during the Reading interval and the contribution of a noise component includes, and wherein the during of the read interval applied to the memory unit of the memory Level of the stimulus affects the parameter value, reducing the contribution the noise component is reduced.

A nonvolatile memory according to the invention comprises a memory unit, a sense amplifier connected to the memory unit for determining the state of the memory unit in response to a set of read voltages (V _aper , V _per ) and drivers connected to the memory unit for applying the set of read voltages to the memory unit, the set of read voltages comprising: a read voltage state (V _aper ) and a time varying excitation stimulus voltage state (V _per ), the time varying excitation stimulus voltage state being different from the read voltage state.

According to the present Invention will provide methods for further reducing the reading of a nonvolatile Inherent to memory device Amount of noise, with a time-varying excitation stimulus, hereinafter referred to as "episodic Stimulus ", as part of the reading process to one or more ports of the cell is created. additionally to the voltage levels normally applied to the cell as part of the reading process a time-varying voltage can be applied to the cell. In a group of exemplary embodiments, a single Sentence or become several sentences alternating voltages to one or more terminals of a Floating gate memory cell immediately before the signal integration time a reading process or during this created. In other embodiments, any other reproducible external or internal stimuli are applied, which is repeatable and whose averaged effect (from an integration time to the next Integration time) remains sufficiently constant, so that overall gives a noise reduction effect. Other excitatory stimuli, the can have an overall noise reduction effect, are external or internal generated photons, phonons and magnetic fields.

Further Features and advantages of the present invention will become apparent from the following description of specific representative embodiments which are given by way of example and in which on the attached Drawings reference is made, wherein the

1A -D show examples of the noise behavior in the measured current of a memory cell.

The 2A -C are schematic representations of an interface state trapping site in a floating gate memory cell.

3 shows a simplified embodiment of the present invention.

The 4A D show a specific embodiment of a memory cell structure.

The 5A -C illustrate two special reading processes.

6 shows a further embodiment of a memory cell structure.

The 7A -C illustrate reading processes for the structure 6 ,

The storage capacity of non-volatile semiconductor memories has increased both by reducing the physical size of the individual components of the circuits comprising the memory cell and by increasing the amount of data that can be stored in a single memory cell. For example, components such as those shown in the U.S. Patents 5,712,180 and 6,103,573 as well as in the U.S. Patents 6,426,893 and US 6,522,263 described all of them to SanDisk Corp. transmit four or more logical bits per physical floating gate memory transistor. In the case of 4 logical bits, this memory will require that one of sixteen possible memory states be coded on each floating gate. Each of these memory states corresponds to a unique value, or more specifically, a narrow range of stored charge values on the floating gate, which is sufficiently separated from the charge storage value ranges of the adjacent states to be significantly different from the adjacent states as well as all other states differ. This applies to both a normal read operation and a verify read operation that occurs as part of a program operation.

A number of methods for reading memory cells are in U.S. Patent 6,538,922 and in U.S. Patent 6,747,892 described to SanDisk Corp. are transferred. The first of these applications describes reading the content of the memory cell with a resolution of 7 bits or higher for use in a 4-bit memory. If this number of levels is contained in a 3 volt window of operating voltages, as found in low voltage devices, this results in the requirement for a resolution capability of about 25 mV and a 200 mV separation from state to state. In this range, noise levels that were previously acceptable may now cause the state of the cell to be read with an error of one or more state levels.

The 1A D represent examples of noise fluctuations in reading a memory cell. 1A Fig. 14 shows the case where the value of a certain parameter indicative of the state of the memory cell, in this case the current I (t), fluctuates by a certain average value <I>. In this case, if the signal development time is several times longer than the typical time scale of the fluctuations, a relatively noise-free value for the state of the cell can be determined. The signal development time represents the time interval over which the measurand, which is characteristic for the state of the cell, is developed. The measurand may be the value of the cell drive current, the threshold voltage of the cell, the bit line voltage drop generated in a fixed amount of time, or the time required to generate a fixed amount of bit line voltage drop. Some methods for determining a relatively exact value for the state of the cell are U.S. Patent No. 6,044,019 described from which 1A adapted adopted.

Other reading methods that can be further combined with these other methods are described in a co-pending U.S. Patent entitled "Reducing the Effects of Noise in Non-Volatile Memories Through Multiple Reads" by Carlos J. Gonzalez and Daniel C. Guterman , which was filed simultaneously with the present application and as US 6,621,739 has been granted. Since noise components having different characteristics can be treated with these other methods, they should be considered as complementary to one another and the present invention.

In some cases, it has been found that the noise is not normally distributed in magnitude around a single average, but appears to have a bimodal characteristic, such as in the 1B . 1C and 1D and discussed in the document cited in the Background section [1]. The 1B and 1C show the example of the measured current from a memory cell in which the current varies by a value of, for example, 1 μA, but with a number of peaks of approximately the same amount, for example, 0.10 μA. in 1B the peaks are at a higher current, starting from an underlying, in 1C the peaks are at a lower amperage, and in 1D For example, the higher and lower conductivities determined by the noise source have comparable time characteristics. In all three cases, the duration of these varies stochastically. Both during the time of the peaks and in the period between these there is additional noise in the 1A Since the size of memory devices has shrunk steadily, non-macroscopic effects, such as single electron effects or quantum effects, have become increasingly important and aggravate the problems with noise by introducing these transient spikes that arise in the mesoscopic range , The amount and range of the duration of the peaks will depend on the particular mechanism by which they are created.

When the duration of the peaks is short enough compared to the integration period (ie signal development time) of the reading process, such as in U.S. Patent 6,044,019 or if the peaks occur frequently enough such that, statistically speaking, the same number of noise spikes are present during each integration period, the time-averaged integration time may cause the influence of the noise to become negligible. However, it has been found that in some cases a memory cell may have noise with characteristic time constants that are comparable or substantially longer than those over time which span practical integration periods. In this case, the noise may have an unacceptably strong influence on the resulting read value. For example, with reference to FIG 1D For example, if the integration period is comparable to the typical time during which a noise event manifests itself (eg, a higher current level) or less than this, there will typically be two different read values, depending on when the read will occur he follows. This can severely limit the resolution with which the data content of the cell can be read.

For example, consider a class of applications related to flash memory cells. In observing transistor noise on transistors of various sizes and types (both different-generation flash cells and NMOS transistors), it has been observed (for example, see document [1] from the background) that the magnitude of the noise is inversely proportional to the width of the transistor and can also be related in an analogous manner to the length of the transistor, so that the noise increases with the scaling of the transistor. The threshold voltage, V _TH , of a transistor can be read a few times, and by measuring the various values of V _TH each time the measurement is made, the consequences of the transistor noise can be examined. To measure V _TH using a semiconductor parameter analyzer, various values for the gate / control gate voltage, V _G , can be swept to search for that value for V _G that is at a given drain-to-source value. Current leads (eg 1 μA). When the measurement for V _TH is repeated many times, slightly different values of V _{TH are} found from each measurement. It can also be observed that using longer integration times and / or sweeping V _G with smaller steps does not necessarily or significantly reduce the noise. Alternatively, fixed voltages may be applied to all transistor terminals to make numerous (eg, thousands) repeated DC current measurements. Overall, the current remains roughly constant. However, when observed with a fine resolution scale, fluctuations are detected which often represent unacceptable levels of noise in both analog and nonvolatile multi-level memory cells, especially when the number of memory levels 8th or more (ie three or more bits per cell). It can be seen that a fraction of the memory cells in a memory array are noise-free. This is a consequence of the noise source population in a large sample of device measurements, which tends to correspond to a normal distribution with a characteristic standard deviation. For a device with a behavior like that in the 1B and 1C 12, the transistors will exhibit noise that is normally distributed plus some current values falling out of the normal distribution corresponding to the narrow noise spikes; and for a device with a behavior like that in 1D is shown, the noise will have a distribution that corresponds more to a bimodal than a normal distribution. At certain current levels (corresponding to a particular gate voltage value), many transistors are relatively noise free, and at other current levels they exhibit more noise. Some transistors are noisy at most current levels.

At the Example of a flash cell could at least one source for this noise in so-called interface state traps, (actual interface state trapping sites) consist. Although the methods according to the present invention to reduce noise from many sources in many different ways Systems can be applied should the IST case be discussed in more detail to show how noise can be reduced with these methods, due to of a particular mechanism arises.

Taking the usual term as the basis, much of which is practiced in accordance with the prior art (for example, see document [2] in the background), the term interface state traps is loosely used. Strictly speaking, what are referred to herein as interface states includes not only interface states immediately adjacent to the Si / SiO ₂ interface, but also edge capture sites located in the oxide and up to 30 Å to 40 Å from the surface Are located at the interface. Electrically, both boundary states and interface states (according to strict nomenclature) represent switching states, whereas deep oxide traps represent solid states. Switching states may sometimes be occupied by an electron and may be empty at other times, whereas fixed states at normal operating temperatures tend to maintain their state for long periods of time. In the standard CMOS process and in the process for an EEPROM cell, it is typical to subject the wafer to a hydrogen tempering process. As a result of the hydrogen annealing process, the density of interface state trapping sites at the interface between the substrate and the floating gate oxide can typically be reduced to as low as 1 x 10 ¹⁰ cm ² / eV. Since the bandgap of silicon is about 1 eV, this prior art small value for the density of interface state trapping sites (ISTs) is Means 1 is equal below the gate of each transistor for a gate having a length of 0.1 μm and a width of 0.1 μm. This means that the majority of the flash memory cells in which the extent of the active channel is currently slightly larger than 0.1 μm is affected by one or more ISTs. Thus, no matter how large the value for the given amount of drain / source current corresponding to the definition of V _TH (typically in the wide range of 400 pA to 2 μA), there will always tend to be some transistors at any one selected value for the amperage show an IST-driven noise.

The source of the type of noise to which the present invention is directed is often microscopic (e.g., single atomic defects, interface trapping sites, and free bonds - see document [2] of the Background section, pp. 5060 ff.). The areas of influence of these microscopic defects are mesoscopic in the sense that the electric field lines emanating from a charged trapping site extend over mesoscopic distances (eg, over hundreds of angstroms - see document [3] of the background section, 4 , P. 1032). As electronic devices are miniaturized to sub-micron dimensions, the effects of random capture / release events become more significant as the dimensions of the devices become comparable to the mesoscopic dimensions of the regions of influence of these stochastic microscopic phenomena.

One reason that noise is reduced by the methods of the present invention may be as follows: By applying a varying signal, the memory cell is turned on much harder over shorter intervals than when compared to DC reading. The read signal is developed during the high values of the excitation stimulus, and during these short intervals the memory cell is turned on much harder by driving the cell into a strong inversion. The charge density in the channel is higher at high inversion. That is, the charge of the inversion layer can more effectively shield the field lines emanating from or near a charged trapping site on the SiO ₂ / Si interface. In addition, the stronger the inversion, the thicker the inversion layer and the larger the component of the drain-to-source current that flows in deeper regions from the interface. These lower currents are more largely shielded from the random surface capture / release events.

The 2A and 2 B FIG. 12 illustrates simplified schematic representations of an interface state trap in a generic floating gate transistor. These figures show a floating gate memory from the side in FIG 2A and from the top in 2 B , These show a control gate CG 201 arranged above a floating gate 203 , which in turn is above the channel of the substrate 205 located. When Source S and Drain D are biased and a voltage is applied to the control gate, a current flows between source and drain, the magnitude of which is determined by the amount of charge stored on the floating gate. Viewed from above, the channel area under the two gates has a width W and a length L.

The area between the floating gate FG 203 and the substrate 205 is occupied by the floating gate dielectric. The interface between the dielectric and the substrate results in a discontinuity of the structure on each side of the interface, which may lead to a site for an interface state capture site. The distribution density of such trapping sites in the direction perpendicular to the surface can be determined as a roughly Gaussian distribution with centering at the interface (compare document [4] in the Background section, 2 ). An illustration of such a place is in the 2A and 2 B at 211 shown.

When a site is occupied by an electron, this results in a Coulomb barrier due to the electron-electron repulsion that extends into the channel. As a result, the effective channel width is reduced by an amount ΔW. For example, the peaks at the stochastic peaks are equivalent 1B the electron-release state, and the base current level corresponds to the trapped state. The lifetime of a capture state is related to the distance of the capture site from the nearest conductor (compare document [1], equation 5). The current literature continues to debate the source of change in current that results from capture or release events. The change can be modeled as a change in effective mobility, a change in carrier concentration in the inversion layer, or both (compare documents [1], [5]). One could also model the change in current as a result of changing the effective width, length and / or electric field. A more accurate model would account for a complex three-dimensional device that is dramatically affected by the occupancy state of a single trapping location at the current scaling level. The charge state of the trap can affect any term that occurs in the component current equation (eg, ID = W μ _eff q N _inv E _x from document [5], Equation 1). Even the equation for the current, which may be valid for a small device that is defect free, may no longer be valid for the same small device if it is affected by a trap whose state changes the device current. For equations that are typically used to model the current strength of a device, a unitary structure of the device is assumed in one or more dimensions. If the area of influence of the defect is comparable to the active dimension of the device, otherwise valid assumptions and equations will be invalidated. For a cell with multiple capture sites, the effects of each site will overlap the baseline level.

The behavior of a given trap will depend on the bias conditions used to read the cell. As schematically in 2C is shown is the capture site 211 capacitively coupled to the source (S), drain (D), substrate (Sub), and gate (G), with the coupling of the control gate to the trap typically via an intervening floating gate. The trap can be influenced to varying degrees by changing the level at each of these ports. Many effects of trapping sites can be modeled as conductive islands, as discussed in more detail in document [6].

In an exemplary embodiment, an alternating voltage is applied to one or more terminals of the device immediately prior to or during the signal development time (integration time) of the reading process. Other external stimuli that are repeatable and whose mean effect (from one integration time to the next integration time) remains constant can be used in other implementations. The well-known phenomenon of quantum tunneling represents the mechanism responsible for the capture / release process at deeper edge capture sites, whose connection to the nearest conductor is weak enough to provide a charge localization effect. In terms of resistance to tunneling, this means that the tunneling resistance must be greater than the resistance quantum R _Q = h / (2e ² ) = 12.9 kΩ at barriers thinner than 4 nm, with the dominant tunneling mechanism being direct tunneling as is the case with trapping / releasing at local border traps. Many of the deeper oxide capture sites are also less than 4 nm from the nearest conductor or semiconductor interface. Some examples of the nearest conductor / semiconductor interface are the channel, the bottom of the floating gate, or the bottom of the select gate. A time-varying excitation signal may reduce noise if the discrete energy state of the single trap / defect / contaminant succeeds to the quasi-Fermi level (F _{N, P} ) of the closest conductor communication point by a few k _B T in each Shift cycle of the excitation signal, where k _{B is} the Boltzmann constant and T is the temperature. This is because if the energy required to transfer electrons across the barrier were smaller than k _B T, such a trap would then have very short time constants, which would cause the states to switch frequently during any given integration time, and thus not significantly to noise contribute. This is based on the time averaging principle of the Central Limit Theorem, which will be explained later. The communication point to the nearest conductor is the point in the channel, on the floating gate, the select gate, or the control gate, which is close enough to the trap so that electron tunneling can occur between the trap and this point. For most applications, an energy shift of ± 3k _B T should be sufficient.

If the barrier is not thick enough or the energy barrier is not high enough (ie, if the resistance is less than R _Q ), then tunneling may not be the mechanism of electron communication of the defect with the nearest electrode. This may apply to the edge capture sites which are very close to the interface, or those that lie on the semiconductor side of the interface. It should also be noted that for such trap sites, even though there may not be a physical barrier that provides high resistance, the energy barrier may result from the energy required to confine the charge to a potential well of atomic dimensions. In other words, it is possible that there is no insulating atomic layer (s) between the defect and the nearby electrode; but even in such a case, energy may be required to bring an electron to the defect site or to remove an electron from the defect site. In a given system, this required energy may result from one or both of two different phenomena, namely size quantization and charge quantization. Size quantization gains importance when the dimensions of a potential well are comparable to the Fermi wavelength of the electrons in the well. The charge quantization gains importance when the capacity of a defect becomes so small that the threshold energy of the Coulomb barrier = (e ² / 2C) = the minimum capacitive energy to be overcome when adding an electron to a system of N particles (Document [7], Equation 10) becomes larger than k _B T, where C the total capacity of the trap to the outside environment is. Although the concept of capacity is normally used as a spatially unresolved parameter assigned to macroscopic systems, capacity can also be used in a microscopic regime down to atomic level, as described in document [7]. For the microscopic limit, the capacity may be defined as the amount of work per unit load, ΔV, required to bring a fixed amount of charge, ΔQ, from the vacuum level into the system in question, as described in document [7].

In general, electron tunneling phenomena require two conductors separated by a thin insulator. The two sides of the tunnel path through which noise originates are the trap site / defect itself and any other conductor or semiconductor, such as another trap site, the channel of a transistor, drain, source, gate, or the isolation / semiconductor interface conductive site (eg, the sidewall of a shallow trench isolation area (STI area)). Interface capture sites or edge capture sites along the transistor channel, particularly those closer to the bottlenecks for currents, often contribute primarily to the noise of the transistor. Depending on the type of transistor, the bottleneck for the current along the channel near the source side or, in the case of the embodiments, may be out of the range 4A -D lie in the gap between the floating gate and the selection gate. At room temperature, 6 k _B T are 156 mV. To offset the quasi-Fermi levels on either side of the tunnel path by 156 mV requires much higher voltage excursions at a nearby electrode. In the case of flash memory cells, the control gate may be the electrode of choice for applying the AC (excitation) excitation signal. Consider an AC signal with an amplitude of 1 V applied to the control gate. Of this 1 V, only 0.5 V amplitude is applied to the floating gate (assuming a 50% control gate to floating gate coupling ratio). For a trapping site on the interface that is at a depth of, for example, 1 nm in the oxide and 7.5 nm away from the floating gate (assuming a channel oxide thickness of 9.5 nm), the capacitive coupling efficiency of the floating Gate to the capture site modeled as a spherical conductor with a radius of 5 Å, 10.4%. This result was obtained with solution software for 3D Poisson equations named "Raphael", which was supplied by Avanti Corp. is distributed. The trapping site to channel capacity was calculated to be 2.56 x 10 ^-19 F, the trapping site-floating gate capacity was calculated to be 2.96 x 10 ^-20 F, and the total trapping site capacity became 2.85 x 10 -4 ^{. 19} F calculated. The 5 Å radius for the trapping site is only a well-founded assumption. In addition, the assumption that the relative dielectric constant of the oxide represents a constant value of 3.9 may not be valid in the following sense: the few atomic layers between the trapping site and the trapping site Channel may consist of SiO _x (in contrast to SiO ₂ ). SiO _x has a lower content of elemental oxygen than SiO ₂ , with some oxygen vacancies. SiO _x may have a relative dielectric constant other than SiO ₂ . Moreover, the Poisson equation can lose its validity in such small dimensions. Using the above values for capacitance, it follows that only 50 mV arrive at the trap from a control gate amplitude of 1.0V. Since the channel potential is also changed by the AC signal applied to the control gate, a considerable portion of the amplitude of the signal is wasted because it does not work to create a voltage difference between the trap and the channel. Taking this into account, the calculated voltage will only decrease to below 50 mV. The inefficiencies in applying the necessary voltage excursions to the noise sources (with the aim of changing the potential difference between the two sides of the tunnel barriers) may typically require the application of high voltage excursions (in the range of several volts) to one or more given ones Connections are created so that there is an effective noise reduction. The noise reduction process disclosed in the present application remains valid even when the potential barrier between the capture site and the nearest electrode is such that electrons pass through some mechanism other than tunneling to and from the capture site. The concept of tunneling is useful in explaining the fact that the trapping / releasing time constants extend over many orders of magnitude, ranging from less than one microsecond to many years.

Other examples of episodic excitation stimuli that may have an overall noise reduction effect are externally or internally generated photons, phonons, and magnetic fields. The sources of noise to which the present invention is directed are often of a microscopic nature, encompassing trap sites and atomic defects in any physical area of the device. Stochastic electron / hole tunneling can change the state of a trapping site. Depending on their position, the vacancy or occupancy of a trap will affect the behavior of the device. Because components on mesoscopic dimensions and dar As the size decreases, the effects of even a single trapping site become increasingly important. In future generations, these effects may become such a dominant part of the device's behavior that even a reliable binary operation of very small devices may not be possible. If the time constants associated with changing the state of a trap are on or greater than the signal integration time, the stochastic state transitions of a trap will be a source of noise. However, if sufficiently strong stimuli can be provided at a capture site to alter their condition as needed, applying multiple stimuli to the capture site during a single signal integration time forces the capture site to make multiple independent decisions during each integration time. This can lead to reduced noise of the device since each measurement will consist of several independent sub-measurements. Since trapping sites exhibit memory-like behavior, an alternative to rapidly switching between sub-measurements and stimuli would be to wait between any two sub-measurements for a period of time longer than the trapping site's characteristic time constant. However, this waiting time may in many cases be unreasonably long.

A exemplary embodiment is the system during the integration time by applying a trapezoidal AC signal to the gate an NMOS transistor to stimulate. In this case, the effective Integration time limited to the time during which the gate voltage is high. Due to the nonlinear behavior of the transistor while most of it the fall time, the whole low time and the most part the rise time is the gate voltage below the threshold voltage, and the drain-to-source current is too low to be significantly intermediate Total current contribute. For example, suppose that during ¾ of the integration time no current flow is present. To compensate for this and yet the same average current as in the standard DC case Maintain the gate voltage during the high time so elevated be that value of amperage during the high time 4 times as big as the value of the DC current is.

For example, if there are 10 AC cycles in an integration interval, the following situation can be described: The interface trap sites that contribute to the noise behave like stochastic, fickle micro-floating gates with memory-like characteristics. If the tunneling resistance from the trap to the channel is high enough, the average occupancy / idle time of the trapped charge (s) may be on the order of the integration time or above. In such a case, successive measurements may find the same value for the state of the cell. However, for a measurement that occurs much later (with a delay between them that is longer than the lifetime of the current occupancy state of the capture site), another state of the cell could be detected. The same idea can be extended to a single signal development time (integration time corresponding to a single verification process) in the following way: In one embodiment, multiple AC signals are applied to the control gate of a flash memory cell during a single integration time. As mentioned previously, the high value of these stimuli is slightly higher than the DC read voltage, the low value is a few volts lower than the high value, and the duration of the low value is long enough for the occupancy state of the trap to be the empty state effectively, the occupation state of the capture site is randomized during a high-level period to the occupation state of the capture site during the previous high-time period. In this way, a single signal development time is composed of several partial integration times (high level times) during which the state of the trap is independent of the state of the trap during the previous partial integration time. Therefore, the purpose of the high-level times is to develop the bit line voltage signal overall via the bit line discharge, and the purpose of the intermediate low-level times is to reduce the state of the trap during the one high-level time period Trap state during the next period of high level decoupling or randomization. By the end of the low level time, the trap will be forced to its empty state, and upon application of the high voltage value to the control gate, the trap will make a new random decision as to whether it will be occupied or left empty. Since we are currently considering only trapping sites whose characteristic lifetimes are comparable or longer than the DC integration time, it can be safely assumed that for these trapping sites, the state of the trapping site during each partial integration time is usually for the duration of that partial integration time stays the same. The noise of the cycle-internal measurements remains correlated to the extent that the capture / release lifetimes are comparable to the high-time of the signal. On the other hand, the noise between cycles will not be correlated as long as the low value is significantly lower than the high value and the low level duration the duration of the high level is comparable. The distribution of multiple averaged current AC measurements, obtained by averaging over 10 uncorrelated AC cycles, is compared to the distribution of the same number of averaged DC current measurements, each with the same integration time as in AC Case, have a smaller variance.

It is well known that the variance of behavior in a group consisting of individual elements is larger than the variance of behavior in a group consisting of elements composed of an ensemble of the same elements. This is referred to as the Central Limit Theorem (see pp. 954-955 of the fifth edition of Advanced Engineering Mathematics by Erwin Kreyszig). A variant of a number of variants of the Central Limit Theorem reads as follows: Let X ₁ , X ₂ , ..., X _{n be} independent random variables, with the same distribution function and therefore the same mean value μ and the same standard deviation σ. Let A _n = (X ₁ + X ₂ + ... + X _n ) / n. Then the random variable A _n represents the limit of large n is asymptotically normal. In addition, regardless of the value of n, the mean value of A _n is μ, and the standard deviation of A _n is equal to (1 / √n) σ. This implies that a measure composed of the mean of, for example, 9 independent partial measurements will have a standard deviation that will be three times smaller than the inherent standard deviation of the distribution of each of the partial measurements. In this context, standard deviation and noise are interchangeable. The most central and effective concept presented here is the use of the possibility to reduce noise by averaging over several independent sub-measurements. The voltage excursions (excitation stimuli) at any selected electrode from the DC read voltage for that electrode will preferably fill or empty the trap depending on the sign of the excursions. This effect forces the trap to make a new independent decision on its occupancy state each time the deflection is returned to the reading. If sub-measurements are interleaved with these randomized voltage excursions, each sub-measure will be decoupled from the rest. Thus, the essential role of the episodic excitation stimuli is to decouple the state of the capture site during a partial measurement from the state of the capture site during the next partial measurement. The sign of the displacement can be positive or negative. A negative excursion may be easier to implement, in the sense that bringing the control gate voltage to a value below the DC read voltage will normally turn off the cell current in an n-channel transistor for the duration of the negative excitation stimuli. However, sufficiently high magnitude negative excursions will often require the application of negative voltages to a particular electrode, and this may not be easily implemented in some systems. Alternatively, positive voltage excursions can be used to avoid the use of negative voltages. However, for positive excursions, the n-channel based cell would be turned on much more than desired during the positive excursions, and the read signal would not develop properly during the times the desired DCm read conditions are applied. To fix this problem, any other switch on the path of the transistor current must turn off the cell current during the positive excursions. In the NAND architecture of the embodiment 6 For example, the excitation stimuli may be applied to a selected wordline, in which case the switch may be the existing drain-side select gate, the source-side select gate, a non-selected wordline in the same segment, or a combination thereof. In the case of dual-source gate source side injection (DFGSSI) source-side injection architecture, in the embodiments of FIGS 4A - 4D For example, the excitation stimuli may be applied to a selected control gate (sometimes referred to as a control gate). In this case, the switch may be the select gate (ie, the word line), the transfer gate (the other control gate of the two floating gates, also referred to as the overriding control gate), or both. For any given architecture, either one or more existing transistors on the current path may be used as the mentioned switch (s), or one or more new switching transistors may be designed to perform the task of turning off the current of the device for the duration of the positive excitation stimuli.

There may be restrictions, such as the RC time constants of the lines that apply the AC excitation stimuli, or the power requirements of ½CV ² f. For example, in the case of the DFGSSI architecture in the embodiment, the 4A - 4D can be cycled up and down over a thousand high-frequency control or control gate lines to read the contents of a sector (512 bytes), requiring a relatively large amount of power to complete the multiple AC cycles for the excitation stimuli at each one Verification step of a binary search read to realize. Here are some ways to reduce this problem. The RC time constants of the Leitun Genes which apply the excitation stimuli can be reduced by silicidation of the polysilicon lines by converting typical polysilicon lines into metal lines or by reducing the lengths of local line segments and applying the excitation stimuli only to local segments (using local booster plates or booster lines capacitively coupled to the lines of interest). It has been found that noise can be reduced with the above method although the effective integration time has been cut to a quarter of the DC integration time.

Under DC read conditions, a troublesome trap can either be busy or empty. For the sake of simplicity, consider the case where the quasi-Fermi levels of the electron capture site and the nearby channel are aligned under DC read conditions. In this case, the capture site is vacant 50% of the time (vacant) (ie, P _v = 0.5), and is occupied (occupied) in the remaining 50% of the time (ie Po = 0.5). Furthermore, it is assumed that the tunneling resistance is such that the average occupation time τ _o = 1000 μs. The mean vacancy time for these assumptions will also be τ _v = 1000 μs. Therefore, the average time between the same type of transitions is τ _T = 1000 + 1000 = 2000 μs, where τ _{T is} the mean time from one tunneling event to another tunneling event or from one tunneling event to another tunneling event. Note that due to the Pauli exclusion principle, a tunnel exit event must have occurred between any two tunneling events at the same trap site. Assuming a DC read integration time of 10 μs, it is possible that during a read operation the electron is detected as trapped and in another read it is determined to be released. The probabilities for one or more tunneling events within a DC integration time are quite low. However, if another read is performed a few seconds later, the results of these two reads are uncorrelated. Therefore, there is a high correlation with the state of the capture site (short-term memory of the capture site) within any single DC integration interval and a low correlation between reads performed with longer intermediate periods of time (compared to τ _T ).

Consider the case of AC reading in which the control gate voltage of a flash memory cell is varied 10 times in a trapezoidal pulse train having an amplitude of a few volts and a period of less than 1 μs, so that no loss in reading behavior occurs , The high voltage value of the pulses should be greater than the DC read value so that the current during the high level time is 4 times higher than the current level during the low level time due to a duty cycle of 25%. The low value of the pulses should be sufficiently low to almost guarantee that during each low pulse the electron clears the trap. Thereby, the state of the trap becomes high during each high-level period regardless of the state of the trap during the previous high-level period. For the sake of discussion, assume that every 1V on the control gate has a tenfold effect on the occupancy probability. Thus, when P _o = 0.5 and P _v = 0.5 under DC read conditions, 1 volt more at the control gate Po becomes 0.95 and P _v becomes 0.05. By another volt on the control gate, the probabilities become P _o = 0.995 and P _v = 0.005. If the control gate voltage is reduced by 1 V based on the DC read condition, then Po becomes 0.05 and P _v becomes 0.95. The assumptions of symmetric properties for tunneling to and from the trapping site and the ten-fold change in probability per 1 V are introduced here for ease of explanation. The validity of these assumptions has no impact on the efficiency of the noise reduction process. In the example of interface state capture sites, the Fermi level of interest represents the channel Fermi level at a location in the channel just below the interface state. If the energy level of the capture site is below the Fermi level, the capture site is usually occupied occasionally free. In such cases, the DC read current will be at a certain level for most of the time and will have occasional short-term peaks of short duration. Alternatively, if the energy level of the capture site is above the Fermi level, the capture site is usually unoccupied and occasionally occupied. In such cases, most of the time, the amperage is at a certain underlying and has occasional short-duration spikes of short duration. The more energetically unfavorable it is that a trap event (or release event) occurs, the longer the initial empty (or trap) state remains. The difference ΔE = (E _f -E _i ) = (E _{final -E initial} ) between the total energy E _{i of} the system before the capture / release event and the total energy E _{f of} the system thereafter determines the probability of this event. The larger the ΔE, the less likely the transition event is and the longer the initial state of energy E _i remains. When ΔE is negative, the life of the state E _{i is} short.

The more negative the value ΔE, the shorter the life of the state E _i . ΔE settles at least two components together: 1) the difference in electrostatic energy before and after the transition; 2) the work done by the energy supply to lift an electron across a resistive tunnel barrier, with two different potentials on either side of the barrier. For example, if the electrostatic component of ΔE is much smaller than k _B T but the tunneling resistance R _T is large, then the probability of tunneling per unit time is low and the life of both the occupied and the empty state is long. In such cases, over long periods of time, the current strength is at a certain high value in about half the time and is at a certain low value in half the time, with either frequent or infrequent transitions between the two values, depending on the tunneling resistance the capture site.

Returning to the noise reduction method according to the exemplary embodiment, the alternating signal may have a number of different waveforms including, but not limited to, a sine waveform, a square waveform, or a trapezoidal waveform. Since the response of the cell is non-linear, it is possible that the periodic and non-periodic components of the voltage applied to a terminal combined will not give the same average value as the DC component alone. For example, shows 3 schematically the example of a periodic disturbance (V _per ), which is applied to the gate together with a non-periodic voltage (V _aper ). The combined waveform 307 does not need symmetrical to the level ( 313 ) that would be used to measure the same data state without the AC component. Since the peaks can have a saturating effect if they are too high, the combined waveform is arranged to be sufficiently high and low at the extreme peaks. In addition, no integer number of cycles need be used for the periodic part. As long as the waveform is reproducible for a given condition to be measured and achieves the desired effect, it can be used.

Around the wished Capture / Release operation is exemplified embodiments used a waveform with a 50% duty cycle to decorrelate the reads, since the main effect is at the bottom edge and the top edge of the cycle entry. For this reason, it may be preferable to have a square or trapezoidal wave to use, since with these in comparison to a sinusoidal or Triangular waveform a larger proportion of the duty cycle is at the peak levels. Although with a rectangular waveform the peak values are maximized, has a square wave shape in the Practice the disadvantage of overshoot (Gibbs phenomenon), the undesirable effects in particular on the high side which can have reproducibility. Consequently, it represents a trapezoidal waveform often the best compromise.

Although 3 for the purpose of explanation, it shows that the stimulus is applied to the gate, in other embodiments the stimulus may be applied to another terminal. As in 2C 4, the voltage level at a trap can be changed by changing the voltage at any terminal of the cell that can bring some of that voltage in a preferred manner to one of the two conductive entities on each side of the tunnel interface. For example, it may be applied to the substrate, allowing the stimulus to be applied to many cells simultaneously, and also avoiding interference with read voltages applied to the gate. Further examples are discussed below for various cell formation forms.

The circuits which adjust the various voltages will be part of the decoders and the circuit drivers forming the peripheral elements in the circuit array. These are more detailed in the U.S. Patents 5,172,338 and 5,272,669 as well as in the U.S. Patents 5,712,180 and 6,103,573 and in the U.S. Patents 6,426,893 and US 6,512,263 and will be referred to with multiple floating gates in the context of the embodiment.

Of the State of the storage unit can be determined using a number of different Parameters are determined. In the above examples, the determination the level of stored charge of a cell over one Current Measurement done, the strength of the conductivity same is determined using fixed bias conditions. Alternatively, such determination may be made by determining the threshold voltage with the onset of conductivity using varied bias conditions of the control gate is determined. These methods make a number the more common approaches represents.

Alternatively, the determination could be made dynamically by providing that the drive strength determined by the charge level of the cell controls the rate of discharge of a dynamically held (eg, through a precharge capacitor) read node. By determining the time to reach a given discharge level, the value of the stored charge is determined. In this case, the parameter that is indicative of the state of the cell is a time. This approach is in U.S. Patent No. 6,222,762 and in U.S. Patent Application entitled "Sense Amplifier for Multilevel Non-Volatile Integrated Memory Devices," which has already been incorporated by reference. In another alternative method, the state of the memory unit is determined using the frequency as a parameter, an approach that is described in US Pat U.S. Patent No. 6,044,019 is described.

Approaches with determination of the current intensity are more detailed in U.S. Patent 5,172,338 and may be used in the various embodiments described below. However, in most of the following discussion, a threshold voltage detection approach, V _th , is used (alternatively referred to as voltage confinement) because it improves read resolution, keeps current levels, and hence power associated with massively parallel reads, low and its vulnerability for a high bit line resistance is minimized. The approach with detection of V _th , or stress confinement, is more complete in U.S. Patent No. 6,222,762 explained. Another method of voltage detection, in which the voltage at the source is observed for a fixed drain voltage in response to a given gate voltage, is the source follower technique, which is described, for example, in US Pat U.S. Patent 6,538,922 is described.

One binary Search method or a slower linear search method can be applied to determine the condition of the cell. In such schemes will a read consists of multiple verification operations. Each verification process is a specific DC control gate voltage to put on the cell and check if the cell at the applied value of the control gate voltage is ON or OFF. A row such verification procedures that with intelligently selected Control gate values, will then make the read. each Verification can be done in several different ways, for example, current determination across from Voltage detection, dynamic determination against static Determination and determination of the time to onset compared to the determination a fixed time. Most of these variants are already discussed or quoted. A dynamic determination at fixed time would out of the following sequence of events: 1) Create a desired one Voltage to the control gate and keeping it at this voltage until after finishing the reading; 2) Precharging the bit line to one fixed voltage; 3) enabling the bit line, allowing is that the voltage of the bit line lowered by the cell current becomes; 4) After a fixed period of time has elapsed from the release event is, caching the state of the cell based on it, whether the bit line voltage is above or below a given Value is; 5) The control gate voltage can now either be on it Standby value or can be desired on the next Value, for another verification process, be forced.

In one embodiment, each verification step of the read may be preceded by a single-pulse excitation stimulus, or multiple pulses of the excitation stimulus immediately prior to the beginning of the integration, which may be referred to as preconditioning. Alternatively or additionally, single or multiple pulses may be applied during the integration time as excitation stimuli. Preconditioning alone can have the following advantages: a single preconditioning voltage pulse downwards can put most traps into their empty state. When a greater majority of capture sites are such that, under DC read conditions, their empty-state residence times are longer than the occupied-state residence times and are also comparable or longer than the integration time, one or more negative-going preconditioning pulses may ( e) have a total reducing the noise effect. This may be the case for some insulating materials and some typical DC reading conditions. If a greater plurality of trapping sites are such that under DC read conditions, their occupied residence times are longer than their idle times and are also comparable or longer than the integration time, one or more positive ones may occur Preconditioning pulse (s) have an overall noise reducing effect. This may be the case for some insulating materials and some typical DC reading conditions. Although in some cases materials may tend to favor the negative preconditioning impulses, there are always many exceptions to the rule. On the other hand, one or more sufficiently strong, positive-going preconditioning pulses may have an overall noise-reducing effect, since these may be extensive, to the point of restoring the past states of the first verification process immediately after a programming pulse. Knowing that different trap sites have different parasitic short-term memories, the ability to at least partially restore the short-term conditions just prior to the first verification after the last programming pulse can reduce noise. From measurements of a range of transistors covering different process technologies, it can be observed that the preconditioning of be and that the most effective way to reduce noise is to apply multiple decorrelating pulses during each measurement so that each measurement represents an average of several independent sub-measurements. The larger the number of independent sub-measurements included in each measurement, the lower the noise attributable to the measurement. As already mentioned, if N is the number of partial measurements that each measurement consists of, the noise is reduced by a factor (1 / √N). At N = 9, the amplitude of noise in the measurement of V _{th of} a transistor can be reduced by a factor of 3, based directly on the central limit set. If a factor 10 of noise reduction is required, N should be increased to a value of 100. As can be seen, in some embodiments, this method of noise reduction may be more expensive in terms of the energy required and time required to perform all of these independent measurements. One way to reduce this is to apply the excitation stimuli only to the more sensitive verification steps of a binary search read.

A alternative embodiment based on the idea of repeated reading, as follows: Many Support technologies an Error Control Encoding (ECC), an error in the For example, to read a memory sector. The excitatory stimuli could only be called when re-reading a sector, after the first attempt to read the sector yielded too many mistakes has to be corrected immediately, or corrected at all. alternative can be a single between any two read operations for the sector Decorrelation pulse are applied. After a series of reads The same sector may have been exported in this way noisy cells are identified as those whose conditions from one reading to the next differ. Identifying the address of the noisy cells allows the following two approaches to recover the data: 1) Having knowledge of the addresses of the noisy ones Cells enlarge the possibilities of ECC drastically, adding the degree of required error detection reduced and these skills be redirected to the error correction; 2) different combinations adjacent data states for the intoxicated cells can in the ECC machine is fed until the ECC shows no errors. A grayscale of the states a memory cell allows that the neighbor states for one any state differ from that state by exactly 1 bit, thereby the burden for the ECC on transitions to the next neighboring state, as induced by cell noise can be is further reduced.

According to the im Background cited prior art (compare, for example, the Documents [8], [9], [10] and [11]) has been recognized that by cyclical change the voltage applied to a MOS transistor between strong Inversion and accumulation the 1 / f noise, the strong inversion is reduced, although not in any of the cited Documents a practical noise reduction method for use specified in storage systems. In addition, the various offer Aspects of the present invention represent a further advance in the art Subject area in several ways: 1) the cyclic change of inversion to accumulation represents only a subgroup of the possible variants of voltage amounts and Directions that can be applied as excitation stimulus; 2) a varying voltage represents only one form of excitation stimulus group; 3) according to the prior art is no special practical noise reduction method, whereas the invention of the present patent offers a number of detailed procedures, with which the application of this and many other new ideas for example, non-volatile Saving becomes practical; 4) nowhere in the art the idea that the strongest Noise-reducing effects through the use of multiple excitation stimuli while a single integration period; 5) nowhere in the prior art, the Central Limit Theorem for explaining the Efficiency of several excitation stimuli mentioned. The beyond the state of the art Progress of the present invention is in the generalization of each Type of excitation taking advantage of the central limit theorem for the unlimited reduction of noise at the expense of an averaging larger number from partial measurements, which is not just a generalization to one cyclic change between accumulation and inversion means but also on a cyclical change between the DC operating voltage and any other (higher or higher) lower) value at the gate, a generalization to a cyclic change not only at the gate but at any terminal of a device, a generalization to any kind of electronic component unlike only MOSFETs, as in a number of implementations is specified.

In a preferred embodiment, a trapezoidal waveform is utilized in which the low level time, the rise time, the high level time, and the fall time each make up a quarter of the period of the waveform. The greater the amplitude of the signal, the greater the chance of suppressing noise. The high level of the signal is due to the V _{TH of} the transistor does not and should not greatly exceed the V _TH when the AC signal is applied during the integration interval, as this results in the transistor being fully turned on, regardless of its data state.

In yet another embodiment, where multiple pulses are used whose low value represents the DC read value and whose high value is much higher, these can be applied in a single integration time. This requires the presence of another driver on the cell stream path, for example, a separate selector gate in a NOR architecture. This drive element must be switched off in order to stop the otherwise excessive cell current during the entire time in which the gate voltage is raised significantly above the V _{TH of} the cell. In a NAND architecture, this driver may represent a non-selected wordline in the selected NAND string, the source select transistor, or the drain (bitline) select transistor. In an embodiment with two floating gates according to the 4A - 4D For example, the driver may represent the control (ie, control) gate of the unselected floating gate in a memory unit or the select gate.

This Process means a departure from the prevailing practice of the prior art to reduce noise by calming the system before and after reading. With this technique are high levels of activity possible and turn out to be beneficial as long as the activity is during each Reading period is always reproducible or the period of the associated stimulus much shorter than the integration time is. When the episodic signal is on redproducible Can be synchronized with the integration interval, For example, the period of the signal may be extended so that becomes comparable to the integration time. A synchronization can lead to, that the percentage duration of the high level during an integration interval over different Integration intervals remains constant. It is stated have been that when applying AC signals to the gate or to the Substrate of a transistor noise can be reduced considerably. With AC waveforms that are synchronized with the integration interval, even in one cycle per integration time, the noise is in many cases significantly reduced.

So far, the present discussion has been based on an embodiment in which generic floating gate cells according to the 2A and 2 B but it can also be applied more generally to cells of a different construction, since the various aspects of the present invention do not depend specifically on the type of cell. For example, there are EEPROM cells that contain a select gate in addition to the control gate (eg, the DFGSSI architecture). In particular, in another exemplary embodiment including a select gate, a cell having a multiple floating gate structure is also used. Nonvolatile memory cells with this structure are in the U.S. Patents 5,712,180 and 6,103,573 as well as the U.S. Patents 6,426,893 and US 6,572,263 described. The 4A -D are adapted from U.S. Patent 5,712,180 taken over and show such a cell.

The 4A and 4B show a plan view and a cross-sectional view of an embodiment of a memory cell unit having a plurality of floating gates. As in the cross-sectional view 4B 1 is a channel of the cell between the two source / drain regions of the bit lines BL1 711 and BL2 712 educated. The channel is divided into three sections: a left floating gate channel 761 below the left floating gate FGL12 781 and the left control gate CGL2 771 , a right floating gate channel 763 below the right floating gate FGR12 783 and the right-hand control gate CGR2 773 and, between them, a selection channel 762 below the selection transistor T12 772 ,

As in 4A In this structure, the word lines, such as SG1, cross over 720 , the bitlines, such as BL1 711 and BL2 712 to form the array. The location of the memory cells in the array is then defined by the intersection of these lines; for example, the cell is off 4B with the selection transistor T12 772 along the word lines SG1 720 between BL1 711 and BL2 712 , However, the control gates are now connected along the columns parallel to the bitlines, rather than along the rows as in the more traditional architectures. Thus, when a voltage is applied to the control gate line CGL2 771 is applied, this voltage is not only to the gate of the transistor T12 772 but also to the left control gates of all the cells in the column between the bit lines BL1 711 and BL2 712 , 4C FIG. 12 illustrates a circuit diagram illustrating one embodiment of an array of such memory cells as those of FIGS 4A and 4B represents, where 4C represents an equivalent circuit for these memory cells. The floating gates 781 and 783 The cells can be independently programmed and read. Further details on the operation of such a cell are given in the reference documents.

At the cell of the 4A -C interface state capture sites may be anywhere along the channel at or near the substrate / dielectric interface. This can un one of the floating gates, under the selection gate or in the gaps between the gates, as in the place 799 out 4B , be the case. The point will capacitively with different terminals in different strength 4C as well as being coupled to the substrate. In addition to stimulating by changing the level on the control gates, source, drain, and substrate, the introduction of a select gate provides another port to which an episodic stimulus can be applied. The direct capacitive coupling to the select gate will be strongest for trap sites in the region of the select channel below the select gate, but will also affect locations in the floating gate channel via both edge-field coupling and floating point coupling Gate, which in turn is capacitively coupled to the _{select gate} (C _31L and C _31R in _FIG 4C ). This also applies to memory devices with a single floating gate, which include a selection transistor.

The cells from the 4A -C are matrix-like, arranged as an array, as in 4D is shown. In an exemplary embodiment, an AC keystone signal is applied to the wordlines (eg, on 720 ), which are connected to the selection gates (eg 772 ), or alternatively the AC signal is applied to the substrate instead of to the control gates ( 771 and 773 ). It has been found that modulation of the select gate voltage from a low value of 0 V to a high value of 6 V causes noise reduction for some cells.

Realizing the AC signal on the word lines such as 720 has several advantages. For each sector that is read, which may typically contain hundreds to thousands of cells read in parallel, only one wordline needs to be driven. In the event that the lines which are connected to a column of floating gates (eg the "control lines" such as 771 or 773 ), are driven by a periodic signal, the control lines of all the cells that are read in parallel must be simultaneously controlled up and down. This results in a power consumption of (½ CV ² f) for each line, where f is the frequency of the periodic signal, V is its amplitude and C is the total capacitance of the line. This would result in high power consumption in the case of AC driven control gates. In addition, all unselected cells on the same control lines would be exposed to potentially disturbing conditions.

Again on the 4A - 4D Referring to FIG. 1, another advantage of driving the select gate by applying the episodic stimulus over the wordline is that in a typical read or verify process, the conventional wordline operating voltage is generally at a certain fixed value, for example, 5V, regardless of the read cell data. Thus, it is easily possible to apply a signal having an amplitude of 6 V with a fixed high (6 V) and low (0 V) value. The read voltage at the control gate, on the other hand, is data (state) dependent in many reading methods, such as those described in the applications incorporated by reference above. For low-threshold states of the control gate, a high-amplitude AC signal causes the low value of the signal to become negative. This may be difficult to implement for many components and could potentially introduce interference. There are also other circuit design-related complications in episodic stimulation of the control gates during the integration period of the read process, potentially making the selection gate stimulation potentially easier to implement during the read (integration) time.

Methods for reading memory cells are in U.S. Patent 6,583,922 and in U.S. Patent 6,747,892 and in the reference documents contained in these applications.

When reading a non-volatile memory cell, whether as part of a read or as part of the verify phase of a program operation, there will typically be multiple phases. These include applying voltages to the cell such that it is properly biased to detect or measure its data content, followed by an integration period in which a parameter related to the state of the cell is measured. For an EEPROM cell, the parameter is usually a voltage or the source-drain current, but may also be a time or frequency determined by the state of the cell. An example of an embodiment for the read voltages in this measurement process is shown schematically in FIG 5A shown.

5A shows the voltage level on a bit line of a memory array, for example BL1 711 in 4D , In the first phase, the gate voltages are applied to the cells. In the second phase, the bitlines of the cells to be read are charged to a predetermined level. The integration time represents the third phase, starting at a time t = 0 in which the bit line discharges across the cell and the voltage level drops at a rate that depends on the state of the cell. After a time t = t ' For example, the voltage level on the bit line is measured with respect to a reference level V _ref . When the voltage is at V _ref or above, as with the line 501 , the cell is considered to be in an off state. When the voltage is below V _ref , as in conduction 503 , the cell is considered to be in an on state, and hence it is assumed that the voltage on the control gate is above the threshold voltage of the cell.

By including the noise, this situation becomes more complicated, as in 5B is shown. 5B shows exactly the integration section 5A but with the inclusion of noise for the voltage drop lines 501 and 503 , As both lines show, the noise-based fluctuations can cause erroneous read-out at time t 'when there is a jitter in a direction that would result in erroneous reading. Because the wires 501 and 503 diverge over time, increasing the integration time will result in a greater distance, but at the cost of slower read times. In addition, the extent to which t 'can be extended is limited since the voltages ultimately reach a lowest value. An alternative approach, as described in the patent application entitled "Sense Amplifier for Multilevel Non-Volatile Integrated Memory Devices," is disclosed in US Pat 5C shown. In this variant, the cell is biased such that the insertion point level V _{ref is} at the same value as the second phase bias level. In this way, over time, the off-state ( 501 ) further from the on state ( 503 ), without the two lines reaching a lowest value. Given a sufficient integration time, the on state will reach a lowest value, and the off state will reach a top value if there is enough integration time.

The referring to the 5A The process described above represents only one of many reading methods. Depending on the method used to read the cell, the second reading phase, the precharge phase, may be combined with the first phase. In addition, different methods vary both the parameter being measured and the way it is measured. For example, the one in the method U.S. Patent No. 6,044,019 measured parameters represent a frequency indicative of the total amount of current accumulated during the integration period.

The Process according to the present invention can be based on several types Be implemented in any of these reading methods. For example, in a group of embodiments, a single or periodic stimulus in one of the earlier stages of the reading process be created so that the state of the cell before the beginning of Integration phase is randomized. This could be either before investing the gate voltages or during adjusting the gate voltages or during the precharge phase or a combination of these phases. The integration phase can then without simultaneous exposure to episodic stimulation be executed.

In another group of embodiments, the stimulation is applied during the actual integration phase, either beginning before t = 0 (as in FIGS 5A - 5C given), at an earlier stage, and continuing into the integration phase, or by completely placing the stimulus between t = 0 and t '. In some cases, when the stimulus is completely contained in the integration period, it may become easier to reproduce the disorder. For example, in the case of the cell with two floating gates that could be related to the 4A -D has been described, for a predetermined number of cycles, for example n, a periodic voltage oscillation between the channel on and off conditions to the selection gate 772 during which time the total current flowing over the integration time interval is measured. This results in the read value corresponding to the integration of N independent partial readings of shorter duration, the channel turn-on intervals being adjusted in the periodic voltage approach to the DC read conditions.

Another arrangement of memory cells with floating gates is a NAND architecture, for example, that in U.S. Patent US 2003 002348 is described. In 6 there is shown a NAND array adopted from this application. This figure shows columns with, in this example, four memory cells connected between a pair of selection transistors, so that bit lines BL0 to BIN are formed. The lines SGD_i and SGS_i are connected to the drain and source select transistors of each column, respectively, and the control gates of the memory cells in each row are connected along a given word line WL_i. For example, the cell 601 in column 1, line 1, the bit line BL1 is precharged to a level V _BL , the selection transistors and unselected word lines are set to a forward voltage V _pass sufficient to drive all the transistors in column 1 except 601 to turn on completely, and the selected word line WL1_i is set to a (here data-dependent) read voltage V _WL . The bit line BL1 then discharges at a rate determined by the data content of the memory element 601 is determined.

The greater the amplitude of the signal, the greater the ability to suppress noise. The high level of the signal is determined by the V _{TH of} the transistor and must not greatly exceed the V _TH when the episodic stimulus is applied during the integration interval, as this results in the transistor being fully on regardless of its data state. This limitation can be removed by independently turning off a transistor on the path of the current during the application of stimuli exceeding V _TH , as previously discussed. In a first group of embodiments, pulses are used whose low value is the DC read value and whose high value is much higher, and these can be applied in a single integration time. The driver must be turned off to stop the otherwise excessive cell current during all times when the gate voltage is significantly above the V _{TH of} the cell. This driver may be a non-selected wordline in the NAND leg of the column, the source select transistor, or the drain (bitline) select transistor. This is in the 7A and 7B shown.

7A shows an episodic stimulus consisting of a single trapezoidal pulse applied to the single word line corresponding to the voltage V _WL . The selected word line is held at a normal reading during the precharge and signal development phases, with the stimulus applied during the loading period. The pulse reaches an exemplary value of 8V, a value at which the selected transistor on that wordline would turn on completely and the bitline would quickly discharge, regardless of the data state stored in the transistor. To prevent this, the waveform V _{pass is applied} to one of the other transistors in the column. By placing this other transistor at a voltage well below its threshold during the loading period, it is turned off and the bit line charge is maintained. The other transistors can be left at the standard pass value, here 5V. The resulting voltage on bit line V _BL is shown in the upper waveform. It is initially pre-charged in this example to a value of 0.8V, at which point it begins to drop at a rate determined by the relationship between the state of the selected cell and the read value on the bit line. V _pass is then brought low, allowing V _BL to remain steady while _loading V _WL at 8V. The selected wordline is then returned to its read value, _Vpass is returned to 5V, and signal evolution can continue until the parameter value is captured at t '.

7B resembles the 7A except that now several pulses above the read voltage are applied to the word line. A corresponding set of sinks at _Vpass is used to maintain the level at V _BL as these pulses are applied. The resultant behavior on the bit line is that the drop of V _BL by a set of flat terraces when _Vpass is at 0 V, is interrupted.

7C shows an example of an alternative group of embodiments. In this case, the selection transistors and all unselected word lines are kept at the constant pass value here 5 V, as shown by the constant value of V _pass . The stimulus on the selected word line now represents a series of pulses in which V _WL is brought down from the value to, for example, -6V. As before, the resulting waveform of V _BL remains flat during the pulses, but no additional signal V _{pass is} required because the stimulus performs the two functions of applying the necessary stimulating voltage and turning off the conduction.

Although the discussion has heretofore been focused on embodiments in which EEPROM cells are used for the memory device, it can also be applied to other embodiments in which similarly influenced sources of noise pose a problem, including magnetic and optical media. The present invention can find wide application in all types of device / transistor read operations, including, but not limited to, submicron sub-0.1 micron transistors, single electron transistors, organic / carbon nanotransistors, and molecular transistors. For example, the present invention could also be advantageous for such NROM and MNOS cells as described in U.S. Pat U.S. Patent 5,768,192 from Eitan or U.S. Patent No. 4,630,086 Sato et al. or for such magnetic RAM and FRAM cells as described in U.S. Pat U.S. Patent 5,991,193 by Gallagher et al. or in U.S. Patent No. 5,892,706 by Shimizu et al. are described. For these other types of memory elements, the particular mechanisms for determining the parameter reflecting the state of the element may be different, for example magnetic properties would be measured for a magnetic medium and optical properties would be measured for a CD-ROM or other optical media. however, the subsequent process would simply follow from the above examples. Using this approach, existing material systems that are impractical because they suffer from a high density of noise sources, for example, sites with capture / release transitions at interfaces or on a nuclear scale, become viable technologies for high density storage or for small signal applications. As smaller and smaller devices are produced with continued miniaturization, the stochastic (quantum) behavior of the component's inherent fluctuations becomes more significant, and the present method offers a potential opportunity to reduce the impact of resulting noise in an associated system by increasing its stochastic Nature is eliminated or reduced.

Yet another application of the present invention may be to produce more uniform conduction characteristics (e.g., subject to statistical variations in threshold voltage V _TH ) for very small transistors with significant dopant fluctuation effects. Here, the V _TH may be different for macroscopically identical transistors due to the microscopically varying positions of the dopant. The standard deviation of a sample of such V _TH s obtained under DC conditions can be reduced by taking advantage of the presently disclosed noise reduction method. For example, dopant fluctuation effects may result in excessive variations in the behavior of a group of otherwise identical devices. An example of this would be the increased range of the threshold voltage of a group of transistors that should actually be identical. The effects of dopant fluctuations increase as the dimensions of devices decrease, to the point that there are a few dopant atoms in the active portion of a device. This can lead to inconsistent current densities in scales that approximate the dimensions of the active areas of the device. Different DC voltages applied to the gate or drain of an exemplary device may result in new dominant current routing paths. In other words, by changing bias voltages, the path (s) of least resistance can shift. When different DC biases change the behavior of a device, the time varying of the bias has the same effect as moving to a new device. Again, reference may be made to the Central Limit Theorem to explain the possible reduction in behavioral variance under AC conditions, as opposed to DC conditions.

Other Forms of episodic stimuli that determine the condition of the cell or the The value of the measured parameter can also be used. As already mentioned, are other excitation stimuli, which are an overall noise-reducing Can have effect externally or internally generated photons, phonons, magnetic fields, mechanical vibrations or voltages and thermal stresses. For example, too externally applied alternating electric and magnetic fields used to reduce noise. In particular, a could alternating magnetic field used in a magnetic memory cell which directly affects the cell, or itself in a floating gate cell where it induced the cell over Could affect tensions. An increase the temperature could have a 1 / f noise reduction effect, but it also becomes the increase thermal noise. A cyclic change between different temperatures could be Provide methods for reducing noise. Allow for all these cases the methods according to the present invention Invention it using a periodic or AC stimulus the stationary one or DC characteristic of a memory cell with reduced noise read.

Claims (32)

A method of operating a nonvolatile memory, comprising: applying a set of voltages (V _aper , V _per ) to a memory unit ( 601 ) of the nonvolatile memory during an interval (t), and determining the line characteristics (I, V _BL ) of the memory unit in response to the set of voltages, characterized in that the set of voltages comprises a read voltage state (V _aper ) and a time varying excitation stimulus (V _per ) component other than the read voltage state. The method of claim 1, wherein the step of Determining the line characteristics, measuring a current, voltage, Time and frequency includes. The method of claim 1 or claim 2, wherein the memory unit is a floating gate transistor, and the set of voltages further comprises applying a non-periodic voltage to a first control gate. 201 . 771 ) of the transistor, wherein determining the conduction characteristics comprises measuring a parameter between a first and a second source / drain region (Fig. 205 ) of the transistor during a read interval. The method of claim 3, wherein the episodic Stimulus to either the control gate of the transistor or the substrate of the transistor is applied. The method of claim 3 or claim 4, wherein the floating gate transistor further comprises a select gate ( 772 ) and the episodic stimulus is applied to the selection gate. The method of claim 5, wherein the floating gate transistor has two floating gates, wherein a first control gate ( 771 ) above the first ( 781 ) of the two floating gates and a second control gate ( 783 ) above the second ( 763 ) of the two floating gates, wherein the selection gate ( 772 ) lies between the two control gates. Method according to one of claims 3 to 6, wherein the parameter either the current flowing in a channel region of the floating gate transistor, or a voltage required to produce a given amperage is, represents. Method according to one of claims 3 to 7, wherein the reading interval a first phase and a subsequent second phase, wherein the measurement of a parameter during the second phase and applying a set of read voltage waveforms while the first phase begins. The method of claim 8, wherein the episodic Stimulus during either the first or the second phase is created. Method according to one of claims 1 to 8, wherein the episodic Stimulus represents a voltage that is either a sine waveform, has a rectangular waveform or trapezoidal waveform. Method according to one of the preceding claims, wherein the storage unit either a magnetic memory cell, at which the episodic stimulus is a magnetic field, a molecular transistor memory unit, a one-electron transistor memory unit or a nanotransistor memory unit represents. Method according to one of the preceding claims, wherein determining the line characteristics of the memory unit following Steps includes: Determining the Line Characteristics of Memory unit in response to the set of voltages to first time; and subsequently determining the conduction characteristics the memory unit in response to the set of voltages for the second time, with the episodic stimulus component only during the second time Determination is created. The method of claim 12, wherein the following second determination of the line characteristics of the memory unit in response to a result of error control coding he follows. Method for reading the data content of a non-volatile Storage unit comprising: a method according to a of the preceding claims, where the interval represents a reading interval, the measured characteristic measures a parameter value associated with the Data content of the memory unit during the read interval in Context and includes the contribution of a noise component, and while the while the level of the stimulus applied to the memory unit of the read interval affects the parameter value, thereby increasing the contribution of the noise component reduced. The method of claim 14, wherein the memory unit a floating gate transistor represents and measuring a parameter value, the creation of a non-periodic voltage to a first control gate of the transistor and wherein the parameter between a first and a second source / drain region of the transistor is measured. The method of claim 15, wherein the episodic Stimulus either a periodic voltage waveform or a represents single voltage pulse. The method of claim 16, wherein the episodic Stimulus represents a periodic voltage waveform and where the periodic voltage is either a sine waveform, a square waveform or has a trapezoidal waveform. The method of claim 16 or claim 17, wherein the episodic stimulus represents a periodic voltage waveform and wherein the floating gate transistor further comprising a selection gate and the episodic stimulus to the Selection gate is created. The method of claim 16 or claim 17, wherein the episodic stimulus to the first control gate of the transistor is created. The method of claim 16 or claim 17, wherein the episodic stimulus is applied to the substrate of the transistor becomes. A method according to any one of claims 14 to 20, wherein said applying an episodic stimulus' under Response to a result of an error control coding called becomes. Non-volatile memory, comprising: a storage unit ( 601 ), a sense amplifier connected to the memory unit for determining the state of the memory unit in response to a set of read voltages (V _aper , V _per ) and drivers connected to the memory unit for the set of read voltages to apply the memory unit, characterized in that the set of read voltages comprises: a read voltage state (V _aper ); and a time varying stimulus voltage state (V _per ), wherein the time varying stimulus voltage state is different from the read voltage state. The memory of claim 22, wherein the sense amplifier is through sensing a current strength or a voltage is working. A memory according to claim 22 or claim 23, wherein the memory unit is a floating gate transistor. The memory of claim 24, wherein the episodic Stimulus voltage state to either a control gate of the transistor or the substrate of the transistor is applied. The memory of claim 24, wherein the floating gate transistor further comprising a select gate and the episodic stimulus voltage state is created on the selection gate. The memory of claim 26, wherein the floating gate transistor has two floating gates, the first control gate ( 771 ) over a first ( 781 ) of the two floating gates and a second control gate ( 783 ) above the second ( 763 ) of the two floating gates, wherein the selection gate ( 772 ) lies between the two control gates. A memory according to any one of claims 22 to 26, wherein the parameter either the current flowing in a channel region of the floating gate transistor, or a voltage required to produce a given amperage is, represents. A memory according to any one of claims 22 to 27, wherein the episodic Stimulus-stress state represents a periodic voltage that is either a square waveform or has a trapezoidal waveform. A memory according to any one of claims 22 to 29, comprising an error control code section which with the sense amplifier and coupled with the drivers, the drivers being the episodic Stimulus voltage state in response to a control signal from the error control code section. A memory according to any one of claims 22 to 30, wherein the memory unit either a magnetic memory cell in which the episodic Stimulus is a magnetic field, a molecular transistor storage unit, a one-electron transistor memory unit or a nanotransistor memory unit represents. The memory of any one of claims 22 to 31, wherein the nonvolatile memory an array of memory units, an element of which is the memory unit and wherein it comprises an amplifier line which between one of the drivers and a section of the array is switched which includes the memory unit, thereby causing the episodic stimulus voltage state is created.