DE60206567D1 - Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal - Google Patents

Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal

Info

Publication number
DE60206567D1
DE60206567D1 DE60206567T DE60206567T DE60206567D1 DE 60206567 D1 DE60206567 D1 DE 60206567D1 DE 60206567 T DE60206567 T DE 60206567T DE 60206567 T DE60206567 T DE 60206567T DE 60206567 D1 DE60206567 D1 DE 60206567D1
Authority
DE
Germany
Prior art keywords
data signal
signal
clock recovery
synchronized
decision circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60206567T
Other languages
English (en)
Other versions
DE60206567T2 (de
Inventor
Dr Wedding
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA filed Critical Alcatel SA
Priority to DE60206567T priority Critical patent/DE60206567T2/de
Application granted granted Critical
Publication of DE60206567D1 publication Critical patent/DE60206567D1/de
Publication of DE60206567T2 publication Critical patent/DE60206567T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/113—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using frequency discriminator
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/04—Distributors combined with modulators or demodulators
    • H04J3/047—Distributors with transistors or integrated circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/06—Phase locked loops with a controlled oscillator having at least two frequency control terminals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
DE60206567T 2001-07-09 2002-07-08 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal Expired - Lifetime DE60206567T2 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
DE60206567T DE60206567T2 (de) 2001-07-09 2002-07-08 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE10132403A DE10132403A1 (de) 2001-07-09 2001-07-09 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal
DE10132403 2001-07-09
DE60206567T DE60206567T2 (de) 2001-07-09 2002-07-08 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal

Publications (2)

Publication Number Publication Date
DE60206567D1 true DE60206567D1 (de) 2006-02-23
DE60206567T2 DE60206567T2 (de) 2006-06-22

Family

ID=7690574

Family Applications (2)

Application Number Title Priority Date Filing Date
DE10132403A Withdrawn DE10132403A1 (de) 2001-07-09 2001-07-09 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal
DE60206567T Expired - Lifetime DE60206567T2 (de) 2001-07-09 2002-07-08 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE10132403A Withdrawn DE10132403A1 (de) 2001-07-09 2001-07-09 Verfahren und Vorrichtung zur Taktrückgewinnung aus einem Datensignal

Country Status (4)

Country Link
US (1) US20030007584A1 (de)
EP (1) EP1276270B1 (de)
AT (1) ATE306758T1 (de)
DE (2) DE10132403A1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7408981B2 (en) * 2003-05-20 2008-08-05 Rambus Inc. Methods and circuits for performing margining tests in the presence of a decision feedback equalizer
US7627029B2 (en) 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
US7590175B2 (en) * 2003-05-20 2009-09-15 Rambus Inc. DFE margin test methods and circuits that decouple sample and feedback timing
DE102005018950B4 (de) * 2004-12-01 2011-04-14 Wired Connections LLC, Wilmington Vorrichtung und Verfahren zur Phasensynchronisation mit Hilfe eines Mikrocontrollers
CN111446962B (zh) 2020-04-03 2023-12-12 京东方科技集团股份有限公司 时钟信号产生电路、时钟信号产生方法及电子设备
CN111429826B (zh) * 2020-04-15 2023-06-20 京东方科技集团股份有限公司 一种同步电路及其同步方法、显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212601A (en) * 1991-05-03 1993-05-18 Western Digital Corporation Disk drive data synchronizer with window shift synthesis
EP0614283B1 (de) * 1993-03-01 1997-10-29 Nippon Telegraph And Telephone Corporation Phasenregelkreis mit Abtast- und Halteschaltung
JP2993559B2 (ja) * 1997-03-31 1999-12-20 日本電気株式会社 位相同期回路
FR2793091B1 (fr) * 1999-04-30 2001-06-08 France Telecom Dispositif d'asservissement de frequence
US7095816B2 (en) * 2001-03-07 2006-08-22 Nippon Telegraph And Telephone Corporation Clock/data recovery circuit

Also Published As

Publication number Publication date
DE10132403A1 (de) 2003-01-23
DE60206567T2 (de) 2006-06-22
ATE306758T1 (de) 2005-10-15
EP1276270A3 (de) 2004-05-12
EP1276270A2 (de) 2003-01-15
US20030007584A1 (en) 2003-01-09
EP1276270B1 (de) 2005-10-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: ALCATEL LUCENT, PARIS, FR