DE60200894D1 - Schutzstruktur gegen Störungen - Google Patents

Schutzstruktur gegen Störungen

Info

Publication number
DE60200894D1
DE60200894D1 DE60200894T DE60200894T DE60200894D1 DE 60200894 D1 DE60200894 D1 DE 60200894D1 DE 60200894 T DE60200894 T DE 60200894T DE 60200894 T DE60200894 T DE 60200894T DE 60200894 D1 DE60200894 D1 DE 60200894D1
Authority
DE
Germany
Prior art keywords
protection structure
structure against
against interference
interference
protection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60200894T
Other languages
English (en)
Other versions
DE60200894T2 (de
Inventor
Didier Belot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE60200894D1 publication Critical patent/DE60200894D1/de
Publication of DE60200894T2 publication Critical patent/DE60200894T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203Particular design considerations for integrated circuits
    • H01L27/0248Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE60200894T 2001-02-05 2002-02-04 Schutzstruktur gegen Störungen Expired - Fee Related DE60200894T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0101525 2001-02-05
FR0101525A FR2820547A1 (fr) 2001-02-05 2001-02-05 Structure de protection contre des parasites

Publications (2)

Publication Number Publication Date
DE60200894D1 true DE60200894D1 (de) 2004-09-16
DE60200894T2 DE60200894T2 (de) 2005-09-01

Family

ID=8859625

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60200894T Expired - Fee Related DE60200894T2 (de) 2001-02-05 2002-02-04 Schutzstruktur gegen Störungen

Country Status (4)

Country Link
US (1) US6762462B2 (de)
EP (1) EP1229587B1 (de)
DE (1) DE60200894T2 (de)
FR (1) FR2820547A1 (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2820546B1 (fr) * 2001-02-05 2003-07-11 St Microelectronics Sa Structure de protection contre des parasites

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1200017A (en) * 1981-12-04 1986-01-28 Ho C. Huang Microwave field effect transistor
US5723897A (en) * 1995-06-07 1998-03-03 Vtc Inc. Segmented emitter low noise transistor
JP3131823B2 (ja) * 1996-05-16 2001-02-05 株式会社サンコーシヤ 多端子サージ防護デバイス
FR2787636B1 (fr) * 1998-12-17 2001-03-16 St Microelectronics Sa Dispositif semi-conducteur avec substrat du type bicmos a decouplage de bruit
SE518231C2 (sv) * 2000-05-12 2002-09-10 Ericsson Telefon Ab L M Förfarande för brusfördelning i substrat med hög resistivitet som innefattar differentiell eller balanserad integrerad koppling

Also Published As

Publication number Publication date
US6762462B2 (en) 2004-07-13
EP1229587B1 (de) 2004-08-11
EP1229587A1 (de) 2002-08-07
US20020121649A1 (en) 2002-09-05
DE60200894T2 (de) 2005-09-01
FR2820547A1 (fr) 2002-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee