DE602008003233D1 - Priorisierung von interrupts in einer speichersteuerung - Google Patents

Priorisierung von interrupts in einer speichersteuerung

Info

Publication number
DE602008003233D1
DE602008003233D1 DE602008003233T DE602008003233T DE602008003233D1 DE 602008003233 D1 DE602008003233 D1 DE 602008003233D1 DE 602008003233 T DE602008003233 T DE 602008003233T DE 602008003233 T DE602008003233 T DE 602008003233T DE 602008003233 D1 DE602008003233 D1 DE 602008003233D1
Authority
DE
Germany
Prior art keywords
interrupts
host
storage controller
priorizing
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602008003233T
Other languages
English (en)
Inventor
Brian Dow Clark
Juan Alonso Coronado
Beth Ann Peterson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/772,742 external-priority patent/US7613860B2/en
Priority claimed from US11/772,734 external-priority patent/US7617345B2/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE602008003233D1 publication Critical patent/DE602008003233D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/24—Interrupt
    • G06F2213/2404—Generation of an interrupt or a group of interrupts after a predetermined number of interrupts

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Exchange Systems With Centralized Control (AREA)
DE602008003233T 2007-07-02 2008-06-26 Priorisierung von interrupts in einer speichersteuerung Active DE602008003233D1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/772,742 US7613860B2 (en) 2007-07-02 2007-07-02 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
US11/772,734 US7617345B2 (en) 2007-07-02 2007-07-02 Prioritization of interrupts in a storage controller based on interrupt control directives received from hosts
PCT/EP2008/058148 WO2009003903A1 (en) 2007-07-02 2008-06-26 Prioritization of interrupts in a storage controller

Publications (1)

Publication Number Publication Date
DE602008003233D1 true DE602008003233D1 (de) 2010-12-09

Family

ID=39767043

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602008003233T Active DE602008003233D1 (de) 2007-07-02 2008-06-26 Priorisierung von interrupts in einer speichersteuerung

Country Status (6)

Country Link
EP (1) EP2165264B1 (de)
KR (1) KR101154800B1 (de)
AT (1) ATE486321T1 (de)
BR (1) BRPI0811669B1 (de)
DE (1) DE602008003233D1 (de)
WO (1) WO2009003903A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5076967B2 (ja) * 2008-02-27 2012-11-21 富士通株式会社 情報処理システム、情報処理システムの制御方法、および情報処理システムの制御プログラム
US8023522B2 (en) 2009-03-30 2011-09-20 Intel Corporation Enabling long-term communication idleness for energy efficiency
US8560750B2 (en) * 2011-05-25 2013-10-15 Lsi Corporation Systems and methods for advanced interrupt scheduling and priority processing in a storage system environment
US9535777B2 (en) * 2013-11-22 2017-01-03 Intel Corporation Defect management policies for NAND flash memory
IL239113A (en) 2015-06-01 2016-12-29 Elbit Systems Land & C4I Ltd A system and method for determining audio characteristics from a body

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5542076A (en) * 1991-06-14 1996-07-30 Digital Equipment Corporation Method and apparatus for adaptive interrupt servicing in data processing system
US6615305B1 (en) * 1998-08-27 2003-09-02 Intel Corporation Interrupt pacing in data transfer unit
DE10160298A1 (de) * 2001-12-07 2003-06-18 Bosch Gmbh Robert Verfahren und Vorrichtung zur Verarbeitung von Interrput-Signalen
US7065598B2 (en) * 2002-12-20 2006-06-20 Intel Corporation Method, system, and article of manufacture for adjusting interrupt levels

Also Published As

Publication number Publication date
WO2009003903A1 (en) 2009-01-08
EP2165264B1 (de) 2010-10-27
KR101154800B1 (ko) 2012-07-03
BRPI0811669A2 (pt) 2016-11-08
BRPI0811669B1 (pt) 2020-01-14
EP2165264A1 (de) 2010-03-24
KR20100037099A (ko) 2010-04-08
ATE486321T1 (de) 2010-11-15

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Legal Events

Date Code Title Description
8320 Willingness to grant licences declared (paragraph 23)