DE602007008484D1 - Verfahren und Vorrichtung zur Reduzierung der Seitenersetzungszeit in einem System, das die Seitenabruf-Technik verwendet - Google Patents

Verfahren und Vorrichtung zur Reduzierung der Seitenersetzungszeit in einem System, das die Seitenabruf-Technik verwendet

Info

Publication number
DE602007008484D1
DE602007008484D1 DE602007008484T DE602007008484T DE602007008484D1 DE 602007008484 D1 DE602007008484 D1 DE 602007008484D1 DE 602007008484 T DE602007008484 T DE 602007008484T DE 602007008484 T DE602007008484 T DE 602007008484T DE 602007008484 D1 DE602007008484 D1 DE 602007008484D1
Authority
DE
Germany
Prior art keywords
page
replacement time
reducing
fetch technique
technique
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602007008484T
Other languages
English (en)
Inventor
Ji-Hyun In
Il-Hoon Shin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of DE602007008484D1 publication Critical patent/DE602007008484D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/123—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
    • G06F12/124—Replacement control using replacement algorithms with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list being minimized, e.g. non MRU
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
DE602007008484T 2006-01-13 2007-01-03 Verfahren und Vorrichtung zur Reduzierung der Seitenersetzungszeit in einem System, das die Seitenabruf-Technik verwendet Active DE602007008484D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060004140A KR100772863B1 (ko) 2006-01-13 2006-01-13 요구 페이징 기법을 적용한 시스템에서 페이지 교체 수행시간을 단축시키는 방법 및 장치

Publications (1)

Publication Number Publication Date
DE602007008484D1 true DE602007008484D1 (de) 2010-09-30

Family

ID=37898352

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602007008484T Active DE602007008484D1 (de) 2006-01-13 2007-01-03 Verfahren und Vorrichtung zur Reduzierung der Seitenersetzungszeit in einem System, das die Seitenabruf-Technik verwendet

Country Status (6)

Country Link
US (1) US7953953B2 (de)
EP (1) EP1818832B1 (de)
JP (1) JP4481999B2 (de)
KR (1) KR100772863B1 (de)
CN (1) CN100541455C (de)
DE (1) DE602007008484D1 (de)

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KR101496325B1 (ko) * 2008-01-16 2015-03-04 삼성전자주식회사 가상 머신의 상태를 저장, 복원하는 방법 및 장치
CN101742688A (zh) * 2008-11-26 2010-06-16 三星电子株式会社 移动通信系统中发送寻呼的方法
US8180981B2 (en) * 2009-05-15 2012-05-15 Oracle America, Inc. Cache coherent support for flash in a memory hierarchy
KR101612922B1 (ko) * 2009-06-09 2016-04-15 삼성전자주식회사 메모리 시스템 및 메모리 시스템 관리 방법
US8356141B2 (en) * 2010-06-28 2013-01-15 Hewlett-Packard Development Company, L.P. Identifying replacement memory pages from three page record lists
JP4966418B1 (ja) * 2011-01-26 2012-07-04 株式会社東芝 情報処理装置及び書き込み制御方法
JP5664347B2 (ja) 2011-03-04 2015-02-04 ソニー株式会社 仮想メモリシステム、仮想メモリの制御方法、およびプログラム
US8973144B2 (en) 2011-10-13 2015-03-03 Mcafee, Inc. System and method for kernel rootkit protection in a hypervisor environment
US9069586B2 (en) * 2011-10-13 2015-06-30 Mcafee, Inc. System and method for kernel rootkit protection in a hypervisor environment
US20130219116A1 (en) * 2012-02-16 2013-08-22 Wenguang Wang Data migration for composite non-volatile storage device
US10073851B2 (en) 2013-01-08 2018-09-11 Apple Inc. Fast new file creation cache
US9129674B2 (en) * 2013-06-27 2015-09-08 Intel Corporation Hybrid memory device
KR101477776B1 (ko) * 2013-12-26 2014-12-30 성균관대학교산학협력단 플래시 메모리에서의 페이지 교체 방법
CN103839591A (zh) * 2014-03-05 2014-06-04 福州瑞芯微电子有限公司 存储器自动检错和容错电路及控制方法
EP3153971B1 (de) 2015-10-08 2018-05-23 Huawei Technologies Co., Ltd. Datenverarbeitungsvorrichtung und verfahren zum betrieb einer datenverarbeitungsvorrichtung
US9460011B1 (en) 2015-12-14 2016-10-04 International Business Machines Corporation Memory reference estimation method and device based on improved cache
US10942844B2 (en) 2016-06-10 2021-03-09 Apple Inc. Reserved memory in memory management system
KR102400977B1 (ko) 2020-05-29 2022-05-25 성균관대학교산학협력단 프로세서를 통한 페이지 폴트 처리 방법
CN113722246B (zh) * 2021-11-02 2022-02-08 超验信息科技(长沙)有限公司 处理器中物理内存保护机制的实现方法及装置
CN116661684B (zh) * 2023-05-10 2024-02-23 珠海妙存科技有限公司 一种闪存数据的读取方法、系统、设备及介质

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Also Published As

Publication number Publication date
CN100541455C (zh) 2009-09-16
JP4481999B2 (ja) 2010-06-16
KR20070075640A (ko) 2007-07-24
EP1818832A3 (de) 2008-01-23
KR100772863B1 (ko) 2007-11-02
JP2007188499A (ja) 2007-07-26
EP1818832A2 (de) 2007-08-15
US7953953B2 (en) 2011-05-31
CN101000581A (zh) 2007-07-18
EP1818832B1 (de) 2010-08-18
US20070168627A1 (en) 2007-07-19

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