DE602006020865D1 - Struktur zur formung eines musters für eine funktionelle folie und verfahren zur herstellung der funktionellen folie - Google Patents

Struktur zur formung eines musters für eine funktionelle folie und verfahren zur herstellung der funktionellen folie

Info

Publication number
DE602006020865D1
DE602006020865D1 DE602006020865T DE602006020865T DE602006020865D1 DE 602006020865 D1 DE602006020865 D1 DE 602006020865D1 DE 602006020865 T DE602006020865 T DE 602006020865T DE 602006020865 T DE602006020865 T DE 602006020865T DE 602006020865 D1 DE602006020865 D1 DE 602006020865D1
Authority
DE
Germany
Prior art keywords
functional film
pattern
producing
forming
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006020865T
Other languages
English (en)
Inventor
Yukio Sakashita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujifilm Corp
Original Assignee
Fujifilm Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujifilm Corp filed Critical Fujifilm Corp
Publication of DE602006020865D1 publication Critical patent/DE602006020865D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H10N30/073—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies by fusion of metals or by adhesives
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/074—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N60/00—Superconducting devices
    • H10N60/01—Manufacture or treatment
    • H10N60/0268—Manufacture or treatment of devices comprising copper oxide
    • H10N60/0296—Processes for depositing or forming copper oxide superconductor layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/14—Layer or component removable to expose adhesive
    • Y10T428/1486—Ornamental, decorative, pattern, or indicia

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Laminated Bodies (AREA)
  • Recrystallisation Techniques (AREA)
  • Physical Vapour Deposition (AREA)
  • Manufacturing Of Electric Cables (AREA)
DE602006020865T 2005-06-07 2006-06-05 Struktur zur formung eines musters für eine funktionelle folie und verfahren zur herstellung der funktionellen folie Active DE602006020865D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005166400 2005-06-07
PCT/JP2006/311666 WO2006132379A2 (en) 2005-06-07 2006-06-05 Structure for functional film pattern formation and method of manufacturing functional film

Publications (1)

Publication Number Publication Date
DE602006020865D1 true DE602006020865D1 (de) 2011-05-05

Family

ID=36699297

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006020865T Active DE602006020865D1 (de) 2005-06-07 2006-06-05 Struktur zur formung eines musters für eine funktionelle folie und verfahren zur herstellung der funktionellen folie

Country Status (4)

Country Link
US (1) US20080135162A1 (de)
EP (1) EP1889306B1 (de)
DE (1) DE602006020865D1 (de)
WO (1) WO2006132379A2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1889307B1 (de) * 2005-06-07 2011-04-20 FUJIFILM Corporation Struktur enthaltender funktionaler film und verfahren zur herstellung eines funktionalen films
US20110109203A1 (en) * 2009-11-06 2011-05-12 The Trustees Of Princeton University Flexible piezoelectric structures and method of making same
JP5399970B2 (ja) * 2010-03-31 2014-01-29 パナソニック株式会社 強誘電体デバイスの製造方法
US8592291B2 (en) * 2010-04-07 2013-11-26 Massachusetts Institute Of Technology Fabrication of large-area hexagonal boron nitride thin films
TWI644800B (zh) * 2018-01-15 2018-12-21 國立臺灣師範大學 含有二硫化鉬之生物感測晶片以及應用該生物感測晶片之檢測裝置

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4886573A (en) * 1986-08-27 1989-12-12 Hitachi, Ltd. Process for forming wiring on substrate
US4988674A (en) * 1989-02-09 1991-01-29 Eastman Kodak Company Electrically conductive articles and processes for their fabrication
US6071795A (en) * 1998-01-23 2000-06-06 The Regents Of The University Of California Separation of thin films from transparent substrates by selective optical processing
JP2002134806A (ja) * 2000-10-19 2002-05-10 Canon Inc 圧電膜型アクチュエータおよび液体噴射ヘッドとその製造方法
US6589857B2 (en) * 2001-03-23 2003-07-08 Matsushita Electric Industrial Co., Ltd. Manufacturing method of semiconductor film
FR2830983B1 (fr) * 2001-10-11 2004-05-14 Commissariat Energie Atomique Procede de fabrication de couches minces contenant des microcomposants
CN1263173C (zh) * 2001-12-06 2006-07-05 松下电器产业株式会社 复合压电体及其制造方法
US7439555B2 (en) * 2003-12-05 2008-10-21 International Rectifier Corporation III-nitride semiconductor device with trench structure
US7943491B2 (en) * 2004-06-04 2011-05-17 The Board Of Trustees Of The University Of Illinois Pattern transfer printing by kinetic control of adhesion to an elastomeric stamp
JP4949668B2 (ja) * 2004-12-09 2012-06-13 富士フイルム株式会社 セラミックス膜の製造方法及びセラミックス膜を含む構造物
EP1889307B1 (de) * 2005-06-07 2011-04-20 FUJIFILM Corporation Struktur enthaltender funktionaler film und verfahren zur herstellung eines funktionalen films
WO2006132382A2 (en) * 2005-06-07 2006-12-14 Fujifilm Corporation Method of manufacturing a film
EP1889289B1 (de) * 2005-06-07 2011-03-30 FUJIFILM Corporation Struktur enthaltender funktionaler film und verfahren zur herstellung eines funktionalen films
US20060288928A1 (en) * 2005-06-10 2006-12-28 Chang-Beom Eom Perovskite-based thin film structures on miscut semiconductor substrates

Also Published As

Publication number Publication date
US20080135162A1 (en) 2008-06-12
EP1889306A2 (de) 2008-02-20
WO2006132379A3 (en) 2007-05-03
EP1889306B1 (de) 2011-03-23
WO2006132379A2 (en) 2006-12-14

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DE602006020865D1 (de) Struktur zur formung eines musters für eine funktionelle folie und verfahren zur herstellung der funktionellen folie