DE602006019640D1 - Integrierte schaltung zum unabhängigen betreiben mehrerer kommunikationskanäle - Google Patents
Integrierte schaltung zum unabhängigen betreiben mehrerer kommunikationskanäleInfo
- Publication number
- DE602006019640D1 DE602006019640D1 DE602006019640T DE602006019640T DE602006019640D1 DE 602006019640 D1 DE602006019640 D1 DE 602006019640D1 DE 602006019640 T DE602006019640 T DE 602006019640T DE 602006019640 T DE602006019640 T DE 602006019640T DE 602006019640 D1 DE602006019640 D1 DE 602006019640D1
- Authority
- DE
- Germany
- Prior art keywords
- integrated circuit
- communication channels
- multiple communication
- independent operation
- communication
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Transmitters (AREA)
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Time-Division Multiplex Systems (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/319,855 US7809068B2 (en) | 2005-12-28 | 2005-12-28 | Integrated circuit capable of independently operating a plurality of communication channels |
PCT/US2006/047323 WO2007075328A1 (en) | 2005-12-28 | 2006-12-11 | Integrated circuit capable of independently operating a plurality of communication channels |
Publications (1)
Publication Number | Publication Date |
---|---|
DE602006019640D1 true DE602006019640D1 (de) | 2011-02-24 |
Family
ID=37831742
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE602006019640T Active DE602006019640D1 (de) | 2005-12-28 | 2006-12-11 | Integrierte schaltung zum unabhängigen betreiben mehrerer kommunikationskanäle |
Country Status (7)
Country | Link |
---|---|
US (1) | US7809068B2 (de) |
EP (1) | EP1966710B1 (de) |
CN (1) | CN101310262B (de) |
AT (1) | ATE495495T1 (de) |
DE (1) | DE602006019640D1 (de) |
TW (1) | TWI339796B (de) |
WO (1) | WO2007075328A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7676605B1 (en) * | 2005-04-06 | 2010-03-09 | Teradici Corporation | Methods and apparatus for bridging a bus controller |
US7908335B1 (en) | 2005-04-06 | 2011-03-15 | Teradici Corporation | Methods and apparatus for bridging a USB connection |
US7675931B1 (en) * | 2005-11-08 | 2010-03-09 | Altera Corporation | Methods and apparatus for controlling multiple master/slave connections |
US7826349B2 (en) * | 2006-05-30 | 2010-11-02 | Intel Corporation | Connection management mechanism |
US8392745B2 (en) * | 2010-04-26 | 2013-03-05 | Broadcom Corporation | Modular integrated circuit with clock control circuit |
US8386688B2 (en) * | 2010-04-29 | 2013-02-26 | Broadcom Corporation | Modular integrated circuit with common interface |
US8345459B2 (en) * | 2011-02-10 | 2013-01-01 | Ati Technologies Ulc | Architecture to facilitate reuse in multiple applications |
US8621113B2 (en) * | 2011-05-31 | 2013-12-31 | Micron Technology, Inc. | Apparatus including host bus adapter and serial attachment programming compliant device and related methods |
US9778859B2 (en) | 2013-09-18 | 2017-10-03 | Western Digital Technologies, Inc. | Doorless protocol having multiple queue read requests in flight |
US9547472B2 (en) | 2013-09-18 | 2017-01-17 | HGST Netherlands B.V. | ACK-less protocol for noticing completion of read requests |
Family Cites Families (37)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5247671A (en) | 1990-02-14 | 1993-09-21 | International Business Machines Corporation | Scalable schedules for serial communications controller in data processing systems |
US5293486A (en) | 1991-06-28 | 1994-03-08 | Digital Equipment Corporation | Deterministic method for allocation of a shared resource |
US6542951B1 (en) * | 1999-08-04 | 2003-04-01 | Gateway, Inc. | Information handling system having integrated internal scalable storage system |
US7248592B1 (en) * | 2002-08-14 | 2007-07-24 | Hewlett-Packard Development Company, L.P. | Partitionable data fabric and computing arrangement |
US7231581B2 (en) | 2003-12-31 | 2007-06-12 | Intel Corporation | Communicating using a partial block in a frame |
US20050223141A1 (en) | 2004-03-31 | 2005-10-06 | Pak-Lung Seto | Data flow control in a data storage system |
US20060004935A1 (en) | 2004-06-30 | 2006-01-05 | Pak-Lung Seto | Multi-protocol bridge |
US20060004929A1 (en) * | 2004-06-30 | 2006-01-05 | International Business Machines Corporation | Method and apparatus for recovering from inefficient behavior of devices on I/O buses |
US7272745B2 (en) | 2004-06-30 | 2007-09-18 | Intel Corporation | Data protection system |
US7453904B2 (en) | 2004-10-29 | 2008-11-18 | Intel Corporation | Cut-through communication protocol translation bridge |
US7685350B2 (en) | 2005-06-24 | 2010-03-23 | Intel Corporation | Remote node index mapping mechanism for serial attached storage devices |
US8112564B2 (en) | 2005-06-28 | 2012-02-07 | Intel Corporation | Hard disk drive staggered spin-up mechanism |
US7366817B2 (en) | 2005-06-29 | 2008-04-29 | Intel Corporation | Frame order processing apparatus, systems, and methods |
US20070005850A1 (en) | 2005-06-29 | 2007-01-04 | Intel Corporation | Port multiplier mapping apparatus, systems, and methods |
US7376789B2 (en) | 2005-06-29 | 2008-05-20 | Intel Corporation | Wide-port context cache apparatus, systems, and methods |
US8370581B2 (en) | 2005-06-30 | 2013-02-05 | Intel Corporation | System and method for dynamic data prefetching |
US8135869B2 (en) | 2005-06-30 | 2012-03-13 | Intel Corporation | Task scheduling to devices with same connection address |
US7805543B2 (en) | 2005-06-30 | 2010-09-28 | Intel Corporation | Hardware oriented host-side native command queuing tag management |
US20070011333A1 (en) | 2005-06-30 | 2007-01-11 | Victor Lau | Automated serial protocol initiator port transport layer retry mechanism |
US7970953B2 (en) | 2005-06-30 | 2011-06-28 | Intel Corporation | Serial ATA port addressing |
US7747788B2 (en) | 2005-06-30 | 2010-06-29 | Intel Corporation | Hardware oriented target-side native command queuing tag management |
US8149854B2 (en) | 2005-06-30 | 2012-04-03 | Intel Corporation | Multi-threaded transmit transport engine for storage devices |
US20070005833A1 (en) | 2005-06-30 | 2007-01-04 | Pak-Lung Seto | Transmit buffers in connection-oriented interface |
US20070005898A1 (en) | 2005-06-30 | 2007-01-04 | William Halleck | Method, apparatus and system for task context cache replacement |
US7797463B2 (en) | 2005-06-30 | 2010-09-14 | Intel Corporation | Hardware assisted receive channel frame handling via data offset comparison in SAS SSP wide port applications |
US7221531B2 (en) | 2005-09-12 | 2007-05-22 | Intel Corporation | Staggered spin-up disable mechanism |
US7506080B2 (en) | 2005-09-16 | 2009-03-17 | Inter Corporation | Parallel processing of frame based data transfers |
US7620751B2 (en) * | 2005-09-27 | 2009-11-17 | Intel Corporation | Command scheduling and affiliation management for serial attached storage devices |
US7415549B2 (en) | 2005-09-27 | 2008-08-19 | Intel Corporation | DMA completion processing mechanism |
US7516257B2 (en) | 2005-09-27 | 2009-04-07 | Intel Corporation | Mechanism to handle uncorrectable write data errors |
US7418615B2 (en) | 2005-09-27 | 2008-08-26 | Intel Corporation | Universal timeout mechanism |
US8112507B2 (en) | 2005-09-27 | 2012-02-07 | Intel Corporation | Remote node list searching mechanism for storage task scheduling |
US7451255B2 (en) | 2005-09-28 | 2008-11-11 | Intel Corporation | Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support |
US7664889B2 (en) | 2005-09-29 | 2010-02-16 | Intel Corporation | DMA descriptor management mechanism |
US20070076685A1 (en) | 2005-09-30 | 2007-04-05 | Pak-Lung Seto | Programmable routing for frame-packet based frame processing |
US7676604B2 (en) | 2005-11-22 | 2010-03-09 | Intel Corporation | Task context direct indexing in a protocol engine |
US20070198761A1 (en) | 2005-12-28 | 2007-08-23 | Duerk Vicky P | Connection management mechanism |
-
2005
- 2005-12-28 US US11/319,855 patent/US7809068B2/en not_active Expired - Fee Related
-
2006
- 2006-12-11 EP EP06845251A patent/EP1966710B1/de not_active Not-in-force
- 2006-12-11 AT AT06845251T patent/ATE495495T1/de not_active IP Right Cessation
- 2006-12-11 CN CN2006800428802A patent/CN101310262B/zh not_active Expired - Fee Related
- 2006-12-11 DE DE602006019640T patent/DE602006019640D1/de active Active
- 2006-12-11 WO PCT/US2006/047323 patent/WO2007075328A1/en active Application Filing
- 2006-12-13 TW TW095146704A patent/TWI339796B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
ATE495495T1 (de) | 2011-01-15 |
TW200741467A (en) | 2007-11-01 |
EP1966710B1 (de) | 2011-01-12 |
US7809068B2 (en) | 2010-10-05 |
US20070147522A1 (en) | 2007-06-28 |
CN101310262B (zh) | 2010-06-09 |
EP1966710A1 (de) | 2008-09-10 |
WO2007075328A1 (en) | 2007-07-05 |
TWI339796B (en) | 2011-04-01 |
CN101310262A (zh) | 2008-11-19 |
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