DE602006014084D1 - Cache-kohärenter Split-bus - Google Patents

Cache-kohärenter Split-bus

Info

Publication number
DE602006014084D1
DE602006014084D1 DE602006014084T DE602006014084T DE602006014084D1 DE 602006014084 D1 DE602006014084 D1 DE 602006014084D1 DE 602006014084 T DE602006014084 T DE 602006014084T DE 602006014084 T DE602006014084 T DE 602006014084T DE 602006014084 D1 DE602006014084 D1 DE 602006014084D1
Authority
DE
Germany
Prior art keywords
cache
bus
coherent
split
coherent split
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006014084T
Other languages
English (en)
Inventor
Fong Pong
Lief O'donnell
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Broadcom Corp
Original Assignee
Broadcom Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Broadcom Corp filed Critical Broadcom Corp
Publication of DE602006014084D1 publication Critical patent/DE602006014084D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/4045—Coupling between buses using bus bridges where the bus bridge performs an extender function
DE602006014084T 2006-01-31 2006-10-05 Cache-kohärenter Split-bus Active DE602006014084D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/344,411 US7475176B2 (en) 2006-01-31 2006-01-31 High bandwidth split bus

Publications (1)

Publication Number Publication Date
DE602006014084D1 true DE602006014084D1 (de) 2010-06-17

Family

ID=38090816

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006014084T Active DE602006014084D1 (de) 2006-01-31 2006-10-05 Cache-kohärenter Split-bus

Country Status (5)

Country Link
US (2) US7475176B2 (de)
EP (1) EP1814038B1 (de)
CN (1) CN100587680C (de)
DE (1) DE602006014084D1 (de)
TW (1) TWI382313B (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7475176B2 (en) * 2006-01-31 2009-01-06 Broadcom Corporation High bandwidth split bus
US7937520B2 (en) * 2008-01-11 2011-05-03 Mediatek Inc. General purpose interface controller of resoure limited system
US8214592B2 (en) * 2009-04-15 2012-07-03 International Business Machines Corporation Dynamic runtime modification of array layout for offset
CN105260331B (zh) * 2015-10-09 2018-08-28 天津国芯科技有限公司 一种双总线内存控制器

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2746530B2 (ja) * 1993-01-30 1998-05-06 洲 植 全 共有メモリマルチプロセッサ
US5897667A (en) * 1993-11-16 1999-04-27 Intel Corporation Method and apparatus for transferring data received from a first bus in a non-burst manner to a second bus in a burst manner
US5701422A (en) * 1995-12-13 1997-12-23 Ncr Corporation Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
EP1189141A3 (de) * 2000-09-13 2005-12-28 Texas Instruments Inc. Busbrücke
JP2002304369A (ja) * 2001-04-04 2002-10-18 Nec Corp バスシステム
US6801977B2 (en) * 2002-01-07 2004-10-05 International Business Machines Corporation Method and apparatus for passing messages through a bus-to-bus bridge while maintaining ordering
US7305410B2 (en) * 2002-12-26 2007-12-04 Rocket Software, Inc. Low-latency method to replace SQL insert for bulk data transfer to relational database
EP1581862A2 (de) * 2002-12-30 2005-10-05 Koninklijke Philips Electronics N.V. Verfahren zum buszugriff in einem gruppierten befehlsebenen-parallel-prozessor
US7305510B2 (en) * 2004-06-25 2007-12-04 Via Technologies, Inc. Multiple master buses and slave buses transmitting simultaneously
US7532636B2 (en) * 2005-10-07 2009-05-12 Intel Corporation High bus bandwidth transfer using split data bus
US7475176B2 (en) 2006-01-31 2009-01-06 Broadcom Corporation High bandwidth split bus

Also Published As

Publication number Publication date
US20090113096A1 (en) 2009-04-30
US7475176B2 (en) 2009-01-06
TW200821845A (en) 2008-05-16
US20070180176A1 (en) 2007-08-02
EP1814038A3 (de) 2008-01-02
CN100587680C (zh) 2010-02-03
CN101075221A (zh) 2007-11-21
US7904624B2 (en) 2011-03-08
TWI382313B (zh) 2013-01-11
EP1814038B1 (de) 2010-05-05
EP1814038A2 (de) 2007-08-01

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition