DE602006010147D1 - System und Verfahren zur Steuerung der Übertragung von Verarbeitungsvorgangsinformationen - Google Patents

System und Verfahren zur Steuerung der Übertragung von Verarbeitungsvorgangsinformationen

Info

Publication number
DE602006010147D1
DE602006010147D1 DE602006010147T DE602006010147T DE602006010147D1 DE 602006010147 D1 DE602006010147 D1 DE 602006010147D1 DE 602006010147 T DE602006010147 T DE 602006010147T DE 602006010147 T DE602006010147 T DE 602006010147T DE 602006010147 D1 DE602006010147 D1 DE 602006010147D1
Authority
DE
Germany
Prior art keywords
processing operation
information
controlling
transmission
operation information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602006010147T
Other languages
English (en)
Inventor
Hanes Gordon
Brian Mcbride
Laura Mihaela Serghi
David James Wilson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Original Assignee
Alcatel Lucent SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel Lucent SAS filed Critical Alcatel Lucent SAS
Publication of DE602006010147D1 publication Critical patent/DE602006010147D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Information Transfer Between Computers (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
DE602006010147T 2005-09-06 2006-09-05 System und Verfahren zur Steuerung der Übertragung von Verarbeitungsvorgangsinformationen Active DE602006010147D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/221,073 US20070055839A1 (en) 2005-09-06 2005-09-06 Processing operation information transfer control systems and methods

Publications (1)

Publication Number Publication Date
DE602006010147D1 true DE602006010147D1 (de) 2009-12-17

Family

ID=37492040

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602006010147T Active DE602006010147D1 (de) 2005-09-06 2006-09-05 System und Verfahren zur Steuerung der Übertragung von Verarbeitungsvorgangsinformationen

Country Status (5)

Country Link
US (1) US20070055839A1 (de)
EP (1) EP1760580B1 (de)
CN (1) CN1945541A (de)
AT (1) ATE447738T1 (de)
DE (1) DE602006010147D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
RU2312388C2 (ru) * 2005-09-22 2007-12-10 Андрей Игоревич Ефимов Способ организации многопроцессорной эвм
US7631125B2 (en) 2005-09-30 2009-12-08 Intel Corporation Dynamically migrating channels
KR100679050B1 (ko) * 2005-12-12 2007-02-06 삼성전자주식회사 태스크간 빠른 문맥 교환을 위해 레지스터 문맥을 저장,복구하는 방법 및 장치
JP4476267B2 (ja) * 2006-10-06 2010-06-09 株式会社日立製作所 プロセッサ及びデータ転送ユニット
DE102009037235A1 (de) * 2008-10-14 2010-04-15 Giesecke & Devrient Gmbh Speicherverwaltung in einem portablem Datenträger
US9396089B2 (en) 2014-05-30 2016-07-19 Apple Inc. Activity tracing diagnostic systems and methods
US9619012B2 (en) * 2014-05-30 2017-04-11 Apple Inc. Power level control using power assertion requests
US11983537B1 (en) * 2022-12-21 2024-05-14 Ceremorphic, Inc. Multi-threaded processor with power granularity and thread granularity

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6233599B1 (en) * 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US6092175A (en) * 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6408325B1 (en) * 1998-05-06 2002-06-18 Sun Microsystems, Inc. Context switching technique for processors with large register files
US20010042187A1 (en) * 1998-12-03 2001-11-15 Marc Tremblay Variable issue-width vliw processor
US20070055852A1 (en) 2005-09-06 2007-03-08 Alcatel Processing operation management systems and methods

Also Published As

Publication number Publication date
US20070055839A1 (en) 2007-03-08
CN1945541A (zh) 2007-04-11
EP1760580B1 (de) 2009-11-04
ATE447738T1 (de) 2009-11-15
EP1760580A1 (de) 2007-03-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition