DE602004024560D1 - Herstellungsverfahren für Festwert-MOS-Halbleiterspeicherbauelement - Google Patents
Herstellungsverfahren für Festwert-MOS-HalbleiterspeicherbauelementInfo
- Publication number
- DE602004024560D1 DE602004024560D1 DE602004024560T DE602004024560T DE602004024560D1 DE 602004024560 D1 DE602004024560 D1 DE 602004024560D1 DE 602004024560 T DE602004024560 T DE 602004024560T DE 602004024560 T DE602004024560 T DE 602004024560T DE 602004024560 D1 DE602004024560 D1 DE 602004024560D1
- Authority
- DE
- Germany
- Prior art keywords
- memory device
- semiconductor memory
- solid state
- mos semiconductor
- manufacturing solid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000007787 solid Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04425936A EP1675180B1 (de) | 2004-12-22 | 2004-12-22 | Herstellungsverfahren für Festwert-MOS-Halbleiterspeicherbauelement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE602004024560D1 true DE602004024560D1 (de) | 2010-01-21 |
Family
ID=34932947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE602004024560T Active DE602004024560D1 (de) | 2004-12-22 | 2004-12-22 | Herstellungsverfahren für Festwert-MOS-Halbleiterspeicherbauelement |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP1675180B1 (de) |
| DE (1) | DE602004024560D1 (de) |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW490860B (en) | 1998-12-24 | 2002-06-11 | United Microelectronics Corp | Manufacturing of flash memory cell |
| EP1076916A1 (de) * | 1999-02-23 | 2001-02-21 | Actrans System, Inc. | Flash-speicherzelle mit selbst-justierten toren und herstellungsverfahren |
| US6124167A (en) | 1999-08-06 | 2000-09-26 | Micron Technology, Inc. | Method for forming an etch mask during the manufacture of a semiconductor device |
| US6413818B1 (en) * | 1999-10-08 | 2002-07-02 | Macronix International Co., Ltd. | Method for forming a contoured floating gate cell |
| US6791142B2 (en) * | 2001-04-30 | 2004-09-14 | Vanguard International Semiconductor Co. | Stacked-gate flash memory and the method of making the same |
-
2004
- 2004-12-22 EP EP04425936A patent/EP1675180B1/de active Active
- 2004-12-22 DE DE602004024560T patent/DE602004024560D1/de active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP1675180A1 (de) | 2006-06-28 |
| EP1675180B1 (de) | 2009-12-09 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |