DE602004016947D1 - Addressgenerator für einen Verschachtelungsspeicher und einen Entschachtelungsspeicher - Google Patents

Addressgenerator für einen Verschachtelungsspeicher und einen Entschachtelungsspeicher

Info

Publication number
DE602004016947D1
DE602004016947D1 DE602004016947T DE602004016947T DE602004016947D1 DE 602004016947 D1 DE602004016947 D1 DE 602004016947D1 DE 602004016947 T DE602004016947 T DE 602004016947T DE 602004016947 T DE602004016947 T DE 602004016947T DE 602004016947 D1 DE602004016947 D1 DE 602004016947D1
Authority
DE
Germany
Prior art keywords
memory
address
maximum allowable
allowable value
nesting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE602004016947T
Other languages
English (en)
Inventor
Anders Berkeman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telefonaktiebolaget LM Ericsson AB
Original Assignee
Telefonaktiebolaget LM Ericsson AB
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget LM Ericsson AB filed Critical Telefonaktiebolaget LM Ericsson AB
Publication of DE602004016947D1 publication Critical patent/DE602004016947D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation
    • H03M13/2764—Circuits therefore
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2742—Irregular interleaver wherein the permutation pattern is not obtained by a computation rule, e.g. interleaver based on random generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/275—Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/276—Interleaving address generation

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Error Detection And Correction (AREA)
  • Storage Device Security (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
DE602004016947T 2004-03-10 2004-03-10 Addressgenerator für einen Verschachtelungsspeicher und einen Entschachtelungsspeicher Expired - Lifetime DE602004016947D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04005627A EP1575175B1 (de) 2004-03-10 2004-03-10 Addressgenerator für einen Verschachtelungsspeicher und einen Entschachtelungsspeicher

Publications (1)

Publication Number Publication Date
DE602004016947D1 true DE602004016947D1 (de) 2008-11-20

Family

ID=34814279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004016947T Expired - Lifetime DE602004016947D1 (de) 2004-03-10 2004-03-10 Addressgenerator für einen Verschachtelungsspeicher und einen Entschachtelungsspeicher

Country Status (9)

Country Link
US (1) US7873800B2 (de)
EP (1) EP1575175B1 (de)
JP (1) JP4777971B2 (de)
KR (1) KR101274394B1 (de)
CN (1) CN1930782B (de)
AT (1) ATE410830T1 (de)
DE (1) DE602004016947D1 (de)
HK (1) HK1097358A1 (de)
WO (1) WO2005091509A1 (de)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2454194A (en) * 2007-10-30 2009-05-06 Sony Corp Address generation polynomial and permutation matrix for DVB-T2 1k OFDM sub-carrier mode interleaver
US8885761B2 (en) 2003-03-25 2014-11-11 Sony Corporation Data processing apparatus and method
US8179954B2 (en) * 2007-10-30 2012-05-15 Sony Corporation Odd interleaving only of an odd-even interleaver when half or less data subcarriers are active in a digital video broadcasting (DVB) standard
GB2454196B (en) 2007-10-30 2012-10-10 Sony Corp Data processsing apparatus and method
GB2454195A (en) * 2007-10-30 2009-05-06 Sony Corp Address generation polynomial and permutation matrix for DVB-T2 16k OFDM sub-carrier mode interleaver
GB2454193B (en) 2007-10-30 2012-07-18 Sony Corp Data processing apparatus and method
PL2056549T3 (pl) * 2007-10-30 2013-04-30 Sony Corp Urządzenie i sposób przetwarzania danych
DK2056471T3 (da) * 2007-10-30 2009-11-30 Sony Corp Databehandlingsapparat og fremgangsmåde
EP2204002B1 (de) 2007-10-30 2013-05-01 Sony Corporation Vorrichtung und Verfahren zur Datenverarbeitung
GB2454722B (en) * 2007-11-16 2012-10-24 Sony Corp Data processing apparatus and method
GB2460459B (en) * 2008-05-30 2012-07-11 Sony Corp Data processing apparatus and method
US8775750B2 (en) 2009-09-16 2014-07-08 Nec Corporation Interleaver with parallel address queue arbitration dependent on which queues are empty
GB2491377A (en) 2011-05-31 2012-12-05 British Broadcasting Corp Method and apparatus for memory access in an interleaver
US9183057B2 (en) * 2013-01-21 2015-11-10 Micron Technology, Inc. Systems and methods for accessing memory
TWI551079B (zh) * 2014-11-28 2016-09-21 晨星半導體股份有限公司 適用於第二代地面數位視訊廣播系統之解交錯程序之資料處理電路及方法
EP3376673B1 (de) * 2015-11-10 2022-06-29 Sony Group Corporation Datenverarbeitungsvorrichtungen und datenverarbeitungsverfahren zur frequenzverschachtelung und -entschachtelung
US10140223B2 (en) * 2016-06-27 2018-11-27 Qualcomm Incorporated System and method for odd modulus memory channel interleaving

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2577999B2 (ja) * 1989-09-28 1997-02-05 クラリオン株式会社 擬似雑音符号発生装置における先頭又は任意ビットパルス生成回路およびサンプリングパルス生成回路
US5687325A (en) * 1996-04-19 1997-11-11 Chang; Web Application specific field programmable gate array
US6625234B1 (en) * 1998-12-10 2003-09-23 Nortel Networks Limited Efficient implementations of proposed turbo code interleavers for third generation code division multiple access
US6314534B1 (en) * 1999-03-31 2001-11-06 Qualcomm Incorporated Generalized address generation for bit reversed random interleaving
KR100480286B1 (ko) * 1999-04-02 2005-04-06 삼성전자주식회사 터보 인터리빙 어드레스 발생 장치 및 방법
US6549998B1 (en) * 2000-01-14 2003-04-15 Agere Systems Inc. Address generator for interleaving data
JP4555454B2 (ja) * 2000-11-21 2010-09-29 富士通株式会社 データ再生装置
US6871270B2 (en) * 2001-12-03 2005-03-22 Samsung Electronics Co., Ltd. Device and method for minimizing puncturing-caused output delay
US6851039B2 (en) * 2002-09-30 2005-02-01 Lucent Technologies Inc. Method and apparatus for generating an interleaved address

Also Published As

Publication number Publication date
WO2005091509A1 (en) 2005-09-29
CN1930782B (zh) 2012-05-02
JP2007528169A (ja) 2007-10-04
EP1575175B1 (de) 2008-10-08
HK1097358A1 (en) 2007-06-22
CN1930782A (zh) 2007-03-14
US20070139428A1 (en) 2007-06-21
ATE410830T1 (de) 2008-10-15
KR101274394B1 (ko) 2013-06-18
JP4777971B2 (ja) 2011-09-21
KR20070015539A (ko) 2007-02-05
US7873800B2 (en) 2011-01-18
EP1575175A1 (de) 2005-09-14

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Legal Events

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