DE60143275D1 - Vorrichtung und Verfahren zur Durchführung eines kryptographischen Algorithmus - Google Patents
Vorrichtung und Verfahren zur Durchführung eines kryptographischen AlgorithmusInfo
- Publication number
- DE60143275D1 DE60143275D1 DE60143275T DE60143275T DE60143275D1 DE 60143275 D1 DE60143275 D1 DE 60143275D1 DE 60143275 T DE60143275 T DE 60143275T DE 60143275 T DE60143275 T DE 60143275T DE 60143275 D1 DE60143275 D1 DE 60143275D1
- Authority
- DE
- Germany
- Prior art keywords
- mix columns
- coprocessor
- cpu
- cryptographic algorithm
- transformation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000009466 transformation Effects 0.000 abstract 4
- 238000004364 calculation method Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30029—Logical and Boolean instructions, e.g. XOR, NOT
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/003—Countermeasures against attacks on cryptographic mechanisms for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/002—Countermeasures against attacks on cryptographic mechanisms
- H04L9/005—Countermeasures against attacks on cryptographic mechanisms for timing attacks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/04—Masking or blinding
- H04L2209/046—Masking or blinding of operations, operands or results of the operations
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
- H04L2209/12—Details relating to cryptographic hardware or logic circuitry
- H04L2209/125—Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Storage Device Security (AREA)
- Circuits Of Receivers In General (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/EP2001/009583 WO2003019357A1 (en) | 2001-08-20 | 2001-08-20 | Apparatus and method for performing a cryptographic algorithm |
Publications (1)
Publication Number | Publication Date |
---|---|
DE60143275D1 true DE60143275D1 (de) | 2010-11-25 |
Family
ID=8164554
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60143275T Expired - Lifetime DE60143275D1 (de) | 2001-08-20 | 2001-08-20 | Vorrichtung und Verfahren zur Durchführung eines kryptographischen Algorithmus |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP1419436B1 (de) |
AT (1) | ATE484794T1 (de) |
DE (1) | DE60143275D1 (de) |
WO (1) | WO2003019357A1 (de) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW527783B (en) * | 2001-10-04 | 2003-04-11 | Ind Tech Res Inst | Encryption/deciphering device capable of supporting advanced encryption standard |
KR100594265B1 (ko) | 2004-03-16 | 2006-06-30 | 삼성전자주식회사 | 매스킹 방법이 적용된 데이터 암호처리장치, aes암호시스템 및 aes 암호방법. |
US7949130B2 (en) | 2006-12-28 | 2011-05-24 | Intel Corporation | Architecture and instruction set for implementing advanced encryption standard (AES) |
US8538015B2 (en) | 2007-03-28 | 2013-09-17 | Intel Corporation | Flexible architecture and instruction for advanced encryption standard (AES) |
US8787565B2 (en) | 2007-08-20 | 2014-07-22 | Intel Corporation | Method and apparatus for generating an advanced encryption standard (AES) key schedule |
US8624624B1 (en) | 2011-08-26 | 2014-01-07 | Lockheed Martin Corporation | Power isolation during sensitive operations |
US8525545B1 (en) | 2011-08-26 | 2013-09-03 | Lockheed Martin Corporation | Power isolation during sensitive operations |
-
2001
- 2001-08-20 AT AT01976117T patent/ATE484794T1/de not_active IP Right Cessation
- 2001-08-20 DE DE60143275T patent/DE60143275D1/de not_active Expired - Lifetime
- 2001-08-20 EP EP01976117A patent/EP1419436B1/de not_active Expired - Lifetime
- 2001-08-20 WO PCT/EP2001/009583 patent/WO2003019357A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2003019357A1 (en) | 2003-03-06 |
EP1419436B1 (de) | 2010-10-13 |
EP1419436A1 (de) | 2004-05-19 |
ATE484794T1 (de) | 2010-10-15 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE602006008599D1 (de) | Verfahren zum Schutz von IC-Karten vor Leistungsanalyse-Attacken | |
EP2207087B1 (de) | Verfahren zum Schutz einer kryptografischen Vorrichtung gegen SPA-, DPA- und Zeitangriffe | |
CN1989726B (zh) | 用于执行加密计算的方法和装置 | |
DE602004031729D1 (de) | Gerät und verfahren für auswählbare hardware-beschleuniger in einer datengesteuerten architektur | |
DE60313519D1 (de) | Verfahren zur Erzeugung eines Schlüssels, Inhaltsbereitstellungsverfahren, Entschlüsselungsverfahren für verschlüsselte Inhalte, Verfahren zur Erkennung von illegalen Benutzern, System zum Bereitstellen von Inhalten, Benutzersystem, Verfahren zur Ablaufverfolgung, Verschlüsselungsgerät, Entschlüsselungsgerät, und Computerprogramm | |
DE60001393T2 (de) | Verfahren zur überwachung des programmablaufs | |
EP2637349A2 (de) | Kryptographieverarbeitungsvorrichtung | |
DE69736744D1 (de) | Vorrichtung und Verfahren zur Dynamischen Verschlüsselung | |
BR0213057A (pt) | Sistema, dispositivo portátil e método para autentificação, criptografia e assinatura digitais, através da geração de chaves criptográficas de curta duração | |
JP2008295109A (ja) | シークレットキーを使った暗号化計算方法、及び、装置 | |
CA2578316A1 (en) | Table splitting for cryptographic processes | |
ATE447737T1 (de) | Verfahren zum schutz einer kryptographischen einheit mittels homographischer maskierung | |
RU2011149646A (ru) | Устройство обработки шифрования/дешифрования, способ обработки шифрования/дешифрования, устройство обработки информации и компьютерная программа | |
DE60143275D1 (de) | Vorrichtung und Verfahren zur Durchführung eines kryptographischen Algorithmus | |
Wiemers et al. | Entropy reduction for the correlation-enhanced power analysis collision attack | |
EP3291478A1 (de) | Software-schutz gegen differenzielle fehleranalyse | |
RU2003131278A (ru) | Способ шифрования данных | |
Ambrose et al. | A smart random code injection to mask power analysis based side channel attacks | |
DE602004011965D1 (de) | Verfahren und schaltung zum identifizieren und/oder verifizieren von hardware und/oder software eines geräts und eines mit dem gerät arbeitenden datenträgers | |
WO2005067414A3 (en) | System and method for high speed reversible data encryption | |
TW200512648A (en) | Microprocessor apparatus and method for performing block cipher cryptographic functions | |
Maro | Modelling of power consumption for Advanced Encryption Standard and PRESENT ciphers | |
Bucci et al. | Testing power-analysis attack susceptibility in register-transfer level designs | |
TW200517948A (en) | Microprocessor apparatus and method for employing configurable block cipher cryptographic algorithms | |
TWI268689B (en) | Apparatus and method for performing transparent cipher feedback mode cryptographic functions |