DE60132328D1 - Bestimmung des minimum- oder des maximumwertes in einem datensatz - Google Patents
Bestimmung des minimum- oder des maximumwertes in einem datensatzInfo
- Publication number
- DE60132328D1 DE60132328D1 DE60132328T DE60132328T DE60132328D1 DE 60132328 D1 DE60132328 D1 DE 60132328D1 DE 60132328 T DE60132328 T DE 60132328T DE 60132328 T DE60132328 T DE 60132328T DE 60132328 D1 DE60132328 D1 DE 60132328D1
- Authority
- DE
- Germany
- Prior art keywords
- record
- minimum
- determining
- maximum value
- maximum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/22—Indexing scheme relating to groups G06F7/22 - G06F7/36
- G06F2207/222—Binary data tree
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Complex Calculations (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US532510 | 2000-03-21 | ||
US09/532,510 US6931424B1 (en) | 2000-03-21 | 2000-03-21 | Storage efficient minimization logic |
PCT/US2001/008948 WO2001071483A2 (en) | 2000-03-21 | 2001-03-21 | Determinaton of a minimum or maximum value in a set of data |
Publications (2)
Publication Number | Publication Date |
---|---|
DE60132328D1 true DE60132328D1 (de) | 2008-02-21 |
DE60132328T2 DE60132328T2 (de) | 2009-01-08 |
Family
ID=24122100
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE60132328T Expired - Lifetime DE60132328T2 (de) | 2000-03-21 | 2001-03-21 | Bestimmung des minimum- oder des maximumwertes in einem datensatz |
Country Status (6)
Country | Link |
---|---|
US (1) | US6931424B1 (de) |
EP (1) | EP1290542B1 (de) |
AU (1) | AU2001245894A1 (de) |
DE (1) | DE60132328T2 (de) |
TW (1) | TW550497B (de) |
WO (1) | WO2001071483A2 (de) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7167531B2 (en) * | 2001-09-17 | 2007-01-23 | Digeo, Inc. | System and method for shared decoding using a data replay scheme |
US7161994B2 (en) * | 2001-09-17 | 2007-01-09 | Digeo, Inc. | System and method for shared decoding |
US20030133519A1 (en) * | 2001-09-17 | 2003-07-17 | Manish Shah | Forward tracing decoder apparatus and method |
US7103868B2 (en) * | 2002-11-12 | 2006-09-05 | Lsi Logic Corporation | Optimizing depths of circuits for Boolean functions |
US7072922B2 (en) * | 2002-12-13 | 2006-07-04 | Lsi Logic Corporation | Integrated circuit and process for identifying minimum or maximum input value among plural inputs |
US7434034B2 (en) * | 2004-09-13 | 2008-10-07 | Ati Technologies Inc. | SIMD processor executing min/max instructions |
JP4502223B2 (ja) * | 2007-12-05 | 2010-07-14 | 株式会社エスグランツ | ビット列のマージソート装置、方法及びプログラム |
JP4464459B1 (ja) * | 2009-03-29 | 2010-05-19 | 株式会社エスグランツ | コード列検索装置、検索方法及びプログラム |
US20200110579A1 (en) * | 2018-10-05 | 2020-04-09 | International Business Machines Corporation | Argmax function analog circuit |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4100532A (en) * | 1976-11-19 | 1978-07-11 | Hewlett-Packard Company | Digital pattern triggering circuit |
US4821290A (en) * | 1988-02-09 | 1989-04-11 | General Electric Company | Decoder for digital signal codes |
JPH04180124A (ja) * | 1990-11-15 | 1992-06-26 | Toshiba Corp | ソート処理装置 |
US5187675A (en) | 1991-09-18 | 1993-02-16 | Ericsson-Ge Mobile Communications Holding Inc. | Maximum search circuit |
US5383142A (en) * | 1993-10-01 | 1995-01-17 | Hewlett-Packard Company | Fast circuit and method for detecting predetermined bit patterns |
US5455825A (en) * | 1994-04-28 | 1995-10-03 | Mitsubishi Electric Research Laboratories | Tag-based scheduling system for digital communication switch |
US5710562A (en) * | 1995-08-31 | 1998-01-20 | Ricoh Company Ltd. | Method and apparatus for compressing arbitrary data |
-
2000
- 2000-03-21 US US09/532,510 patent/US6931424B1/en not_active Expired - Lifetime
-
2001
- 2001-03-21 WO PCT/US2001/008948 patent/WO2001071483A2/en active IP Right Grant
- 2001-03-21 EP EP01918871A patent/EP1290542B1/de not_active Expired - Lifetime
- 2001-03-21 DE DE60132328T patent/DE60132328T2/de not_active Expired - Lifetime
- 2001-03-21 AU AU2001245894A patent/AU2001245894A1/en not_active Abandoned
- 2001-03-21 TW TW090106603A patent/TW550497B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1290542B1 (de) | 2008-01-09 |
AU2001245894A1 (en) | 2001-10-03 |
WO2001071483A2 (en) | 2001-09-27 |
DE60132328T2 (de) | 2009-01-08 |
WO2001071483A3 (en) | 2002-03-14 |
TW550497B (en) | 2003-09-01 |
US6931424B1 (en) | 2005-08-16 |
EP1290542A2 (de) | 2003-03-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |