DE60117705D1 - Prozessor zur Viterbi-Decodierung - Google Patents

Prozessor zur Viterbi-Decodierung

Info

Publication number
DE60117705D1
DE60117705D1 DE60117705T DE60117705T DE60117705D1 DE 60117705 D1 DE60117705 D1 DE 60117705D1 DE 60117705 T DE60117705 T DE 60117705T DE 60117705 T DE60117705 T DE 60117705T DE 60117705 D1 DE60117705 D1 DE 60117705D1
Authority
DE
Germany
Prior art keywords
processor
viterbi decoding
viterbi
decoding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60117705T
Other languages
English (en)
Other versions
DE60117705T2 (de
Inventor
Masao Ikekawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE60117705D1 publication Critical patent/DE60117705D1/de
Publication of DE60117705T2 publication Critical patent/DE60117705T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6561—Parallelized implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4107—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing add, compare, select [ACS] operations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6563—Implementations using multi-port memories
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6566—Implementations concerning memory access contentions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6569—Implementation on processors, e.g. DSPs, or software implementations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4161—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management
    • H03M13/4169—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing path management using traceback

Landscapes

  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)
  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
DE60117705T 2001-01-15 2001-12-05 Viterbi-Decodierungsprozessor Expired - Lifetime DE60117705T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2001006066A JP3984790B2 (ja) 2001-01-15 2001-01-15 ビタビ復号処理装置
JP2001006066 2001-01-15
PCT/JP2001/010624 WO2002056480A1 (fr) 2001-01-15 2001-12-05 Decodeur de viterbi

Publications (2)

Publication Number Publication Date
DE60117705D1 true DE60117705D1 (de) 2006-05-04
DE60117705T2 DE60117705T2 (de) 2006-08-17

Family

ID=18874020

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60117705T Expired - Lifetime DE60117705T2 (de) 2001-01-15 2001-12-05 Viterbi-Decodierungsprozessor

Country Status (5)

Country Link
US (1) US20040054958A1 (de)
EP (1) EP1355431B1 (de)
JP (1) JP3984790B2 (de)
DE (1) DE60117705T2 (de)
WO (1) WO2002056480A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4408783B2 (ja) * 2004-09-29 2010-02-03 Ｎｅｃエレクトロニクス株式会社 復号装置及び復号方法
KR101127333B1 (ko) * 2007-10-26 2012-03-29 콸콤 인코포레이티드 최적화된 비터비 디코더 및 ｇｎｓｓ 수신기

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3237267B2 (ja) * 1992-07-23 2001-12-10 松下電器産業株式会社 演算装置
US5440504A (en) * 1993-02-19 1995-08-08 Matsushita Electric Industrial Co., Ltd. Arithmetic apparatus for digital signal processor
JP3092534B2 (ja) * 1996-12-13 2000-09-25 日本電気株式会社 ブロックｉｉｒプロセッサ
JP3338374B2 (ja) * 1997-06-30 2002-10-28 松下電器産業株式会社 演算処理方法および装置
US5987490A (en) * 1997-11-14 1999-11-16 Lucent Technologies Inc. Mac processor with efficient Viterbi ACS operation and automatic traceback store
JP3336986B2 (ja) * 1999-02-03 2002-10-21 日本電気株式会社 信号処理プロセッサ及びそれに用いる丸め機能付き積和演算器
US6601215B1 (en) * 2000-02-01 2003-07-29 Agere Systems Inc. Traceback buffer management for VLSI Viterbi decoders

Also Published As

Publication number Publication date
DE60117705T2 (de) 2006-08-17
EP1355431A4 (de) 2005-06-22
US20040054958A1 (en) 2004-03-18
JP2002217747A (ja) 2002-08-02
EP1355431B1 (de) 2006-03-08
WO2002056480A1 (fr) 2002-07-18
JP3984790B2 (ja) 2007-10-03
EP1355431A1 (de) 2003-10-22

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