DE60101248D1 - Zwischenspeicherzelle mit Maskierung und gleicher Anzahl von N-Kanal Transistoren und P-Kanal Transistoren - Google Patents

Zwischenspeicherzelle mit Maskierung und gleicher Anzahl von N-Kanal Transistoren und P-Kanal Transistoren

Info

Publication number
DE60101248D1
DE60101248D1 DE60101248T DE60101248T DE60101248D1 DE 60101248 D1 DE60101248 D1 DE 60101248D1 DE 60101248 T DE60101248 T DE 60101248T DE 60101248 T DE60101248 T DE 60101248T DE 60101248 D1 DE60101248 D1 DE 60101248D1
Authority
DE
Germany
Prior art keywords
channel transistors
masking
same number
buffer cell
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60101248T
Other languages
English (en)
Inventor
Richard Ferrant
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Application granted granted Critical
Publication of DE60101248D1 publication Critical patent/DE60101248D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
DE60101248T 2000-09-04 2001-09-03 Zwischenspeicherzelle mit Maskierung und gleicher Anzahl von N-Kanal Transistoren und P-Kanal Transistoren Expired - Lifetime DE60101248D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0011242A FR2813698B1 (fr) 2000-09-04 2000-09-04 Cellule cache a masquage

Publications (1)

Publication Number Publication Date
DE60101248D1 true DE60101248D1 (de) 2003-12-24

Family

ID=8853941

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60101248T Expired - Lifetime DE60101248D1 (de) 2000-09-04 2001-09-03 Zwischenspeicherzelle mit Maskierung und gleicher Anzahl von N-Kanal Transistoren und P-Kanal Transistoren

Country Status (4)

Country Link
US (1) US6995997B2 (de)
EP (1) EP1187142B1 (de)
DE (1) DE60101248D1 (de)
FR (1) FR2813698B1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2342575A1 (en) * 2001-04-03 2002-10-03 Mosaid Technologies Incorporated Content addressable memory cell
US6888730B2 (en) 2001-04-03 2005-05-03 Mosaid Technologies Incorporated Content addressable memory cell
US7136308B2 (en) * 2004-11-01 2006-11-14 Sun Microsystems, Inc. Efficient method of data transfer between register files and memories
FR2888387A1 (fr) 2005-07-05 2007-01-12 St Microelectronics Sa Cellule de memoire cam associative et matrice de memoire cam constituee d'un reseau de telles cellules de memoire
HUE041930T2 (hu) * 2007-03-27 2019-06-28 Basf Se Eljárás diizocianátok színtelen izocianurátjainak elõállítására
US9947406B2 (en) * 2015-02-23 2018-04-17 Qualcomm Incorporated Dynamic tag compare circuits employing P-type field-effect transistor (PFET)-dominant evaluation circuits for reduced evaluation time, and related systems and methods
CN111564167B (zh) * 2020-04-22 2023-04-07 中国科学院上海微系统与信息技术研究所 存储单元、晶体管的制备方法及存储单元的制备方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01220293A (ja) * 1988-02-29 1989-09-01 Nec Corp 連想記憶回路
WO1994024672A1 (en) * 1993-04-19 1994-10-27 Oki Electric Industry Co., Ltd. Circuit for decoding variable-length code, and system for decoding variable-length code which uses the circuit
US5422838A (en) * 1993-10-25 1995-06-06 At&T Corp. Content-addressable memory with programmable field masking
JPH087580A (ja) * 1994-06-23 1996-01-12 Hitachi Ltd 半導体記憶装置および情報処理装置
JP3191737B2 (ja) * 1997-08-29 2001-07-23 日本電気株式会社 ルータを有するネットワークシステムおよび改良されたルータおよびそのルータに用いられる連想メモリ
US6044005A (en) * 1999-02-03 2000-03-28 Sibercore Technologies Incorporated Content addressable memory storage device
US6480931B1 (en) * 1999-11-05 2002-11-12 International Business Machines Corporation Content addressable storage apparatus and register mapper architecture
US6341079B1 (en) * 2001-05-23 2002-01-22 International Business Machines Corporation Content addressable memory device

Also Published As

Publication number Publication date
US20040252536A1 (en) 2004-12-16
EP1187142B1 (de) 2003-11-19
EP1187142A1 (de) 2002-03-13
US6995997B2 (en) 2006-02-07
FR2813698A1 (fr) 2002-03-08
FR2813698B1 (fr) 2002-11-29

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Legal Events

Date Code Title Description
8332 No legal effect for de