DE60002094D1 - System und verfahren für adressrundfunksynchronisation mit einer mehrzahl von schaltern - Google Patents

System und verfahren für adressrundfunksynchronisation mit einer mehrzahl von schaltern

Info

Publication number
DE60002094D1
DE60002094D1 DE60002094T DE60002094T DE60002094D1 DE 60002094 D1 DE60002094 D1 DE 60002094D1 DE 60002094 T DE60002094 T DE 60002094T DE 60002094 T DE60002094 T DE 60002094T DE 60002094 D1 DE60002094 D1 DE 60002094D1
Authority
DE
Germany
Prior art keywords
switch
sources
address
address request
requests
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60002094T
Other languages
English (en)
Inventor
H Marmash
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Application granted granted Critical
Publication of DE60002094D1 publication Critical patent/DE60002094D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17356—Indirect interconnection networks
    • G06F15/17368—Indirect interconnection networks non hierarchical topologies
    • G06F15/17375—One dimensional, e.g. linear array, ring

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Small-Scale Networks (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Circuits Of Receivers In General (AREA)
  • Two-Way Televisions, Distribution Of Moving Picture Or The Like (AREA)
DE60002094T 1999-08-16 2000-08-16 System und verfahren für adressrundfunksynchronisation mit einer mehrzahl von schaltern Expired - Lifetime DE60002094D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/374,639 US6567885B1 (en) 1999-08-16 1999-08-16 System and method for address broadcast synchronization using a plurality of switches
PCT/US2000/022563 WO2001013247A2 (en) 1999-08-16 2000-08-16 System and method for address broadcast synchronization using a plurality of switches

Publications (1)

Publication Number Publication Date
DE60002094D1 true DE60002094D1 (de) 2003-05-15

Family

ID=23477631

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60002094T Expired - Lifetime DE60002094D1 (de) 1999-08-16 2000-08-16 System und verfahren für adressrundfunksynchronisation mit einer mehrzahl von schaltern

Country Status (6)

Country Link
US (2) US6567885B1 (de)
EP (1) EP1208440B1 (de)
AT (1) ATE237156T1 (de)
AU (1) AU6911800A (de)
DE (1) DE60002094D1 (de)
WO (1) WO2001013247A2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6567885B1 (en) * 1999-08-16 2003-05-20 Sun Microsystems, Inc. System and method for address broadcast synchronization using a plurality of switches
US6813267B1 (en) * 2000-09-11 2004-11-02 Sun Microsystems, Inc. Tunable broadcast/point-to-point packet arbitration
US20020133652A1 (en) * 2001-03-19 2002-09-19 Tai Quan Apparatus for avoiding starvation in hierarchical computer systems that prioritize transactions
US6826643B2 (en) * 2001-03-19 2004-11-30 Sun Microsystems, Inc. Method of synchronizing arbiters within a hierarchical computer system
US6889343B2 (en) * 2001-03-19 2005-05-03 Sun Microsystems, Inc. Method and apparatus for verifying consistency between a first address repeater and a second address repeater
US6877055B2 (en) 2001-03-19 2005-04-05 Sun Microsystems, Inc. Method and apparatus for efficiently broadcasting transactions between a first address repeater and a second address repeater
US6950893B2 (en) * 2001-03-22 2005-09-27 I-Bus Corporation Hybrid switching architecture
US7376811B2 (en) * 2001-11-06 2008-05-20 Netxen, Inc. Method and apparatus for performing computations and operations on data using data steering
US7548957B1 (en) 2002-05-07 2009-06-16 Oracle International Corporation Method and mechanism for a portal website architecture
US7277924B1 (en) * 2002-05-07 2007-10-02 Oracle International Corporation Method and mechanism for a portal website architecture
JP3770203B2 (ja) * 2002-05-21 2006-04-26 日本電気株式会社 クロスバの高速化方法及びクロスバの高速化方式
US6877056B2 (en) * 2002-06-28 2005-04-05 Sun Microsystems, Inc. System with arbitration scheme supporting virtual address networks and having split ownership and access right coherence mechanism
GB2409306A (en) * 2003-12-20 2005-06-22 Autodesk Canada Inc Data processing network with switchable storage
US7451231B2 (en) * 2005-02-10 2008-11-11 International Business Machines Corporation Data processing system, method and interconnect fabric for synchronized communication in a data processing system
US20060176890A1 (en) * 2005-02-10 2006-08-10 International Business Machines Corporation Data processing system, method and interconnect fabric for improved communication in a data processing system
WO2007029053A1 (en) * 2005-09-09 2007-03-15 Freescale Semiconductor, Inc. Interconnect and a method for designing an interconnect
JP5270077B2 (ja) * 2006-08-18 2013-08-21 富士通株式会社 調停回路、クロスバ、リクエスト選択方法、及び情報処理装置
US8082381B2 (en) * 2008-09-02 2011-12-20 Nvidia Corporation Connecting a plurality of peripherals
US8103803B2 (en) * 2008-11-21 2012-01-24 Nvidia Corporation Communication between a processor and a controller
US8610732B2 (en) * 2008-12-11 2013-12-17 Nvidia Corporation System and method for video memory usage for general system application
US8677074B2 (en) * 2008-12-15 2014-03-18 Nvidia Corporation Shared memory access techniques
US8984206B2 (en) * 2012-10-31 2015-03-17 International Business Machines Corporation Weightage-based scheduling for hierarchical switching fabrics
US8902899B2 (en) 2013-02-08 2014-12-02 International Business Machines Corporation Input buffered switching device including bypass logic
US9311207B1 (en) * 2013-09-12 2016-04-12 Emc Corporation Data storage system optimizations in a multi-tiered environment
US9467396B2 (en) 2014-04-11 2016-10-11 International Business Machines Corporation Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4398176A (en) 1980-08-15 1983-08-09 Environmental Research Institute Of Michigan Image analyzer with common data/instruction bus
US5179552A (en) * 1990-11-26 1993-01-12 Bell Communications Research, Inc. Crosspoint matrix switching element for a packet switch
US5166926A (en) 1990-12-18 1992-11-24 Bell Communications Research, Inc. Packet address look-ahead technique for use in implementing a high speed packet switch
US5513369A (en) 1991-08-05 1996-04-30 Ncr Corporation Star coupler device including means for connecting multiple star couplers together in a cascaded relationship
US5613071A (en) 1995-07-14 1997-03-18 Intel Corporation Method and apparatus for providing remote memory access in a distributed memory multiprocessor system
US5862357A (en) 1996-07-02 1999-01-19 Sun Microsystems, Inc. Hierarchical SMP computer system
US6483844B1 (en) * 1999-05-13 2002-11-19 Advanced Micro Devices, Inc. Apparatus and method for sharing an external memory between multiple network switches
US6567885B1 (en) * 1999-08-16 2003-05-20 Sun Microsystems, Inc. System and method for address broadcast synchronization using a plurality of switches
US7020146B2 (en) * 2001-08-30 2006-03-28 Sun Microsystems, Inc. Broadcast arbitration in a multi-domain device

Also Published As

Publication number Publication date
WO2001013247A3 (en) 2001-08-30
US20030191879A1 (en) 2003-10-09
EP1208440B1 (de) 2003-04-09
AU6911800A (en) 2001-03-13
WO2001013247A2 (en) 2001-02-22
US6567885B1 (en) 2003-05-20
WO2001013247A9 (en) 2001-09-20
EP1208440A2 (de) 2002-05-29
ATE237156T1 (de) 2003-04-15
US6678784B2 (en) 2004-01-13

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: SUN MICROSYSTEMS, INC., SANTA CLARA, CALIF., US

8332 No legal effect for de