DE59308225D1 - Method for recognizing addressing errors in memories for digital binary-coded data words - Google Patents

Method for recognizing addressing errors in memories for digital binary-coded data words

Info

Publication number
DE59308225D1
DE59308225D1 DE59308225T DE59308225T DE59308225D1 DE 59308225 D1 DE59308225 D1 DE 59308225D1 DE 59308225 T DE59308225 T DE 59308225T DE 59308225 T DE59308225 T DE 59308225T DE 59308225 D1 DE59308225 D1 DE 59308225D1
Authority
DE
Germany
Prior art keywords
data words
memories
recognizing
coded data
digital binary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE59308225T
Other languages
German (de)
Inventor
Juergen Ing Grad Storm
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE59308225D1 publication Critical patent/DE59308225D1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1032—Simple parity

Abstract

The data words are written to the memories (SM), after having been supplemented for a specific parity, in such a way that at periodic intervals in the sequence of stored data words one of the data words is supplemented in each case to give in each case the other parity compared with the rest of the data words. During reading, the parity bits of the differently treated data words are inverted. <IMAGE>
DE59308225T 1993-08-10 1993-08-10 Method for recognizing addressing errors in memories for digital binary-coded data words Expired - Fee Related DE59308225D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP93112827A EP0643350B1 (en) 1993-08-10 1993-08-10 Method to detect addressing errors in memories for binary coded data words

Publications (1)

Publication Number Publication Date
DE59308225D1 true DE59308225D1 (en) 1998-04-09

Family

ID=8213160

Family Applications (1)

Application Number Title Priority Date Filing Date
DE59308225T Expired - Fee Related DE59308225D1 (en) 1993-08-10 1993-08-10 Method for recognizing addressing errors in memories for digital binary-coded data words

Country Status (6)

Country Link
EP (1) EP0643350B1 (en)
AT (1) ATE163779T1 (en)
DE (1) DE59308225D1 (en)
DK (1) DK0643350T3 (en)
ES (1) ES2113454T3 (en)
GR (1) GR3026495T3 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE384331T1 (en) 2001-11-12 2008-02-15 Siemens Ag MEMORY TEST

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1047437B (en) * 1975-10-08 1980-09-10 Cselt Centro Studi Lab Telecom PROCEDURE AND DEVICE FOR IN-LINE CONTROL OF SEQUENTIAL LOGICAL MEMORIES OPERATING TIME DIVISION
US4103823A (en) * 1976-12-20 1978-08-01 International Business Machines Corporation Parity checking scheme for detecting word line failure in multiple byte arrays

Also Published As

Publication number Publication date
EP0643350A1 (en) 1995-03-15
ES2113454T3 (en) 1998-05-01
GR3026495T3 (en) 1998-07-31
ATE163779T1 (en) 1998-03-15
DK0643350T3 (en) 1998-09-28
EP0643350B1 (en) 1998-03-04

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee