DE4444231A1 - Data stream decoder e.g. for picture, video and film information - Google Patents

Abstract

The decoder includes a control unit and a data processor which decodes a data stream and performs block to raster conversion. A signal processor calculates inverse quantisation, inverse cosine transformation, frame reconstruction and colour space conversion. The data and signal processors and an internal memory are linked to an external memory access. The signal processor includes arithmetic and multiplexer units but no programme controlled central microprocessor. The signal processor includes separate independent controllers for each process being performed. The control unit coordinates digital picture signal processed by sending start signals to the processors.

Description

The invention relates to a method and a circuit arrangement for Conversion of the YCrCb format into the RGB format (Color space conversion) of image information. The formats are two Standards used in signal processing and the display of image information Find application.

Technical field

Modern coding procedures of video signal compression are based on a block-oriented discrete cosine transform (DCT) of samples or prediction errors of the video signal and a subsequent blockorie quantized DCT coefficients. The blocks are square Form and are arranged in successive rows in the picture.

The samples in the blocks represent according to the recommendation CCIR Rec. 601-2, "Encoding Parameters of Digital Television for Studios", the Study Group 25G / 11 from 1990 the digital luminance signal as well as the digital Color difference signals. If the sampling frequencies of these three signals are the same, all three samples contain the information for one pixel. With others Relationships represent the color difference signals and the color information of several neighboring pixels. The samples of the digital signals are each shown with 8 bit resolution.

In contrast to the block-oriented arrangement of the samples at Transfer of coded video signals takes place the representation of the decoded picture on a monitor line by line. There are three color compos for each pixel nent signals for red, green and blue (R, G, and B signal) required. About that In addition, the RGB format is also suitable for further signal processing steps from Interest. The architecture proposed here is suitable for the implementation of the Data Y of the luminance signal and the samples Cr and Cb of the color difference signals in the three data R, G and B of the color component signals. these can then processed further in blocks or lines. The reordering of the data from a block to a line format is called block-to-raster conversion (BRC) and the conversion from RGB format to YCrCb format and back again as Color space conversion (CSC).  

State of the art

According to the CCIR Rec. 601-2 mentioned above, the data Y of the Lumi nanzsignals and the data Cr and Cb of the two color difference signals corresponding

from the data R ', G' and B 'of the color component signals are implemented. The Entries of the matrix in equation (1) are for realizing an integer Arithmetic chosen. The division by 256 can be done by a job index realize shift by 8 bits.

Rounding errors cannot be excluded with a digital CSC. These result in overflows or underflows from the value range for the results. Therefore, the data after the CSC must be on the desired value range be limited.

The data R ', G' and B 'and Y in equation (1) each have 220 quantization levels in the range [16: 235]. The data Cr and Cb in contrast, 225 quantization levels around the zero signal at 128 im Range of values [16: 240]. For display on an RGB monitor or Further processing in RGB format should data R, G and B of the color compo Take signals every 256 quantization levels in the value range [0: 255].

Equation (1) is the basis for the CSC from YCrCb format to RGB Format. The resolution according to R ′, G ′ and B ′ gives with C = 16237:

The values of the data R ′, G ′ and B ′ must then be reduced by 16 (level shifting) and the results are scaled with D = 255/219 (scaling):

The common solution of equations (2) and (3) then results for the CSC from YCrCb format to RGB format:

Equations (2) and (4) cannot do without multiplications. There this a higher circuit compared to additions or subtractions require effort, the number of multiplications with respect to one cost-effective circuit can be minimized.

The first step is to simplify equations (2) and (4). Here the small matrix entries -40 and -99 can be set to zero. Thereby the number of multiplications decreases and thus the requirements a circuit realization. The error inserted with this is due to the 8 bit Representation of the data negligibly small. It results for the gli (2) and (4) the general form:

Here r, g and b stand as placeholders for R ′, G ′ and B ′ or R, G and B.

Solutions based on equation (5) are already in Application writings described. In L64702 JPEG Coprocessor Technical Manual by LSI-Logic, July 1993 is a color space converter (CSC) with one downstream level shifting and range limiting stage described. The Functions of the color space converter are by the equations

certainly.  

The level shifting level carries out the addition of constant values (e.g. 128) according to equations (2) and (3). In contrast, the Matrix equation of the SAA7192A digital color space converter from the Desktop Video Data Handbook from Philips Semiconductors, 1992 the Equation (2)

The level shifting and scaling procedure to the value range [0: 255] takes place here through a look-up table. This format conversion is especially for Studio recordings provided.

For the CSC it is irrelevant in what context the data on the Sample grid of the image are standing. With a block-oriented coding of the Video signals are the data Y, Cr and Cb in successive rows of Blocks arranged. The edge length of all blocks in a row corresponds to that Line length of the encoded picture. In RGB format one can line by line Data sequence may be desirable. One necessary for reordering the data Block-to-raster conversion (BRC) essentially consists of memory for a series of blocks that is line-oriented after block-oriented writing is read. The sequence of BRC and CSC is interchangeable. Will the CSC be first carried out, the BRC memory contains the data R, G and B for each pixel. Otherwise, the BRC memory contains the data Y, Cr and Cb. The consequence BRC-CSC is more advantageous in terms of lower memory requirements if the data Cr and Cb share the color difference signals for several pixels represent.

Object of the invention

The object of the invention was a method and a circuit arrangement to perform a CSC. The transformation from YCrCb to that RGB format should be in accordance with equation (5). By a appropriate selection of the matrix entries and the summands should be one CSC also according to equations (2) or (4) with the same circuit structure can be performed so that a further scaling, such as  in equation (3), then omitted. The circuit arrangement should therefore also Offer the possibility of a reverse transformation by converting the Coefficients obtained from the equation system.

invention

The object is achieved with the inventive method according to claim 1 and the circuit arrangement according to claim 9 solved. It is characteristic that the multiplications in series in only one multiplier and additions in parallel the multiplications. In the case of the underlying Equation 5, the calculation scheme was rearranged so that the Additions can be performed exactly when the intermediate results are out the previous calculations are available. Advantage of this The method is that an intermediate store is omitted.

Due to the pipelined structure of the process, Circuit arrangement allows that includes only one multiplier. The Circuitry is very advantageous since multipliers are essential have greater circuit complexity than, for example, adders.

drawings

The invention is based on two embodiments with the following Drawings explained. Show it:

Fig. 1 block diagram of the CSC circuitry (Version 1),

Fig. 2 Block diagram of the CSC circuitry (Version 2),

Fig. 3 Timing of the operations of the CSC in the CSC architecture (version 1) of Fig. 1,

Fig. 4 allocation of the data Y _2i, Y _{2i + 1} of the luminance signal and the data Cr and Cb _{i i} the color difference signals to the image point grid for eight adjacent pixels in one line,

Fig. 5 timing of the operations of the CSC for two triples R _2i , R _{2i + 1} , G _2i , G _{2i + 1} , B _2i , B _{2i + 1} from two data Y _2i , Y _{2i + 1} and two data Cr _i , Cb _i from one line in FIG. 4.

Embodiments

The structure of the procedure depends on the operations and Data dependencies of equation (5). This can be done in basic operations decompose two operands each. There are five multiplications:

Ma = aY (6)

M₁₂ = a₁₂Cr (7)

M₂₂ = a₂₂Cr (8)

M₂₃ = a₂₃ · Cb (9)

M₃₃ = a₃₃ · Cb (10)

and seven additions:

r = Ma + M₁₂ + c₁ (11)

g = Ma + M₂₂ + M₂₃ + c₂ (12)

b = Ma + M₃₃ + c₃ (13).

The sequences of the two or three additions in equations (11) to (13) are interchangeable. Accordingly, there are different ones for equation (5) Design variants. In the case of a CSC according to equation (2), one is omitted Multiplication, since in equation (6) a = 1. There are then four multiplications per RGB triple required.

The CSC architecture is connected to the BRC memory. The data Y, Cr and Cb are read line by line from the BRC memory. Should this BRC- Memory also provided for other system tasks this memory can even contain the data of one or more images. In this case, a standard module is suitable. Because of the compared to the Load capacities within a highly integrated circuit of large lines capacity is only a comparatively slow access possible. The data Y, Cr and Cb may be in different memory areas filed. The address calculation therefore takes more time. For the CSC Architecture is therefore an advantage when it comes to temporary storage. He can with the below different records are written and then only the CSC Architecture available.

As in equation (1), the matrix entries in equation (5) are multiplied by a factor of 2 ^m and rounded to whole numbers. m be a positive integer. The products from the matrix and the data vector (Y, Cr, Cb) are either divided individually by 2 ^m or the total or a partial sum of the products of the data vector with a matrix line are divided by 2 ^m . This division is easy to implement with a shift.

In the first embodiment of FIG. 1, the data r, g and b are converted from the data Y, Cr and Cb in accordance with equation (5). The CSC architecture in FIG. 2 represents a variant of the architecture example of FIG. 1, in which the addition sequence from the equations (11) to (13) has been exchanged.

The CSC architectures of Fig. 1 and Fig. 2 each consist of a Multipli Painters 101 and two adders 102, 103 which are connected in a pipeline. The partial products from the multiplication of the matrix entries 107 by the data vector (Y, Cr, Cb) 105 are added in adder 102 . Adder 102 has feedback for the sequential addition of the partial products. For the case a = 1 in equation (6), the data Y can be fed to the adder 102 directly from the buffer 104 . In the second adder 103 the Summan the c₁, c₂ and c₃ 109 are added to the matrix vector product. The buffer 104 contains the data Y, Cr and Cb 105 . Two further memories 106 , 108 , which are designed as read-write memory (register, RAM) or read memory (ROM), contain the matrix entries a, a₁₂, a₂₂, a₂₃ and a₃₃ 107 as well as the summands c₁, c₂ and c₃ 109 . It is also conceivable to combine all three memories 104 , 106 , 108 into one. The sum of adder 103 is limited in limiter 110 to the desired value range of the three RGB data r, g and b 111 . This limiter detects area overflows and area underflows. If necessary, the upper or lower range limit is selected as a replacement for the result from adder 103 .

FIG. 3 shows the timing of the operations of the CSC in the architecture of FIG. 1. Here it is assumed that the multiplication and the additions each have time steps of the same length. If two adders are used, the number of multiplications determines the number of time steps. A CSC then requires five time steps per RGB triple and for the case a = 1 in equation (6) only four time steps.

As an alternative to the solutions in Fig. 1 and Fig. 2, it is also conceivable for the additions 102, 103 and the detection of the crossing to unite len the range of values for the limiter 111 in a common circuit or in two Schaltungstei. This would have the advantage of a more compact solution. However, it would also require more time steps than a solution with separate circuit parts.

The CSC architecture in Fig. 2 has the advantage over that of Fig. 1 that the sums of the partial products of the multiplication of the matrix entries 107 with the data vector (Y, Cr, Cb) 105 with the summands c₁, c₂ and c₃ 109 for several Pixels can be used. This case occurs, for example, when the color difference signals contain the color information for several pixels. According to the definitions of the technical committee of ISO and IEC for the so-called MPEG standard, "Information Technology - Coding of Moving Pictures and associated Audio for Digital Storage media up to about 1.5 Mbit / s", Part 2: Video, Draft International Standard ISO / IEC DIS 11172-1, 1993, two samples Cr and Cb of the color difference signals are provided for four pixels each. The picture is divided into macro blocks for 16 × 16 pixels. A macro block consists of four 8 × 8 blocks for the data Y of the luminance signal and one 8 × 8 block for each data Cr and Cb of the two color difference signals. FIG. 4 shows an example of the assignment of the samples of the luminance signal and the color difference signals Cr and Cb to the pixel grid for eight adjacent pixels in one line. The rows from the data Cr and Cb of the color difference signals are used for two successive rows from the data Y of the luminance signal.

FIG. 5 shows the timing of the operations of the CSC for an MPEG video signal in the architecture of FIG. 2. The CSC for two RGB triples requires six time steps. It is assumed here that the CSC is carried out for a number of neighboring pixels.

The operations of the CSC can either be completely performed for each data series (Fig. 4) of the luminance signal as shown in FIG. 3 and FIG. 5 accepted or the partial products from the multiplication of matrix entries 107 with the data Cr and Cb are stored in a further memory . The second solution has the disadvantage of increased circuit complexity, but the advantage that in every second row the CSC for two RGB triples, the multiplier 101 only requires two time steps and the adder 103 at all. This is advantageous if the CSC is part of a system in which the multiplier 101 and the adder 103 are also used for other tasks. The capacity of the memory depends on the number of data Cr and Cb for a row.

A series of data can be composed of a complete image line or it can consist of the points of a line or column of a block. In the first case, a BRC memory upstream of the CSC is read line by line and the data is written into the buffer 104 . The buffer 104 contains the data of a line or line sections. In the second case, buffer 104 may contain the data for one block. For the block structure according to the MPEG standard, the buffer 104 then contains, for example, the 16 × 16 data Y of the luminance signal and the twice 8 × 8 data Cr and Cb of the two color difference signals.

As a special application example of the CSC, it is conceivable to integrate it into a system in which the decoding of video signals according to the MPEG standard is block-oriented. Two RAMs, each with 8 × 8 data, are available as buffer 104 . These RAMs are available for other decoding tasks. In the CSC, the first memory provides space for the 8 × 8 luminance data of a block and the second space for the corresponding twice 4 × 4 data of the color difference signals. Before the CSC begins, the memories are written, for example, with data from an image memory. No further access to the image memory is then required during the CSC.

Claims (11)

1. A method for the back and forth transformation of image information in YCrCb and RGB format (color space conversion) by calculating a system of transformation equations, characterized in that the multiplications of the system of equations are carried out in series by means of the same multiplier and additions in parallel to the multiplications. 2. The method according to claim 1, characterized in that the, on Results from a multiplication or addition based addition exactly one time step after the corresponding multiplication or Addition are carried out. 3. The method according to claim 2 for calculating the system of transformation equations characterized in that each triple [r, g, b] is calculated in seven time steps as follows: 4. The method according to claim 3, characterized in that the calculation for the following triple [r, g, b] begins in the 6th time step. 5. The method according to claim 2 for calculating the system of transformation equations and a ratio of chrominance to luminance resolution of 1/2, characterized in that two successive triples [r, g, b] are calculated in ten time steps as follows: 6. The method according to claim 5, characterized in that the calculation for the following two triples [r, g, b] begins in the 7th time step. 7. The method according to claim 1, characterized in that the Intermediate results of the multiplication of elements [a, a₁₂,. . . , a₃₃] the Transformation matrix with the chrominance values buffered and the intermediate results via a multiplexer multiple times an adder be fed. 8. The method according to any one of the preceding claims, characterized characterized in that calculated values are limited to a number range will. 9. Circuit arrangement for the forward and backward transformation of image information in YCrCb and RGB format (color space conversion), which is used to calculate a system of transformation equations by means of at least one adder, memory for the coefficients of the system of equations and the image information, and characterizing by only one Multiplier ( 101 ) is formed. 10. Circuit arrangement according to claim 9 for calculating the transformation equation system characterized in that the inputs of the multiplier ( 101 ) with the matrix elements [a, a₁₂,. . . , a₃₃] and the vector [Y, Cr, Cb] containing memory, the output of the multiplier ( 101 ) with a multiplexer input of an adder ( 102 ), the second multiplexer input of which has access to the vector elements [Y, Cr, Cb] and the third Input is fed back to the adder output, and the output of the adder ( 102 ) is connected to an input of an adder ( 103 ), the second input of which has access to the vector elements [c₁, c₂, c₃]. 11. Circuit arrangement according to claim 9 for calculating the transformation equation system characterized in that the inputs of the multiplier ( 101 ) with the matrix elements [a, a₁₂,. . . , a₃₃] and the vector [Y, Cr, Cb] containing memory, the output of the multiplier ( 101 ) is connected to a multiplexer input of two adders ( 102 ) and ( 103 ), and the adder 103 is fed back with its output, access to has the vector elements [c₁, c₂, c₃], and is connected to an input of an adder ( 102 ) which has access to the vector elements [Y, Cr, Cb].