DE4401410A1 - Universal bus logic integrated circuit for two=wire and three=wire buses - Google Patents

Abstract

The universal bus logic has three input lines (10,11,12) coupled to a three-wire logic unit (2) and to a two-wire logic unit (1). Data outputs of both units are received by a switching unit (3), together with control signals (SOUT1,SOUT2) on separate lines (13,14). Transfers of data are made to a memory (4) under the control of a write input (Lin) provided by control signals (17,18) from the input. Data output from the memory is fed to the IC circuit modules (6).

Description

Digital data transfer between microprocessors and integrated circuits (ICs) for control ana loger or digital IC functions is usually realized with the help of bus systems; here the information provided by the microprocessor (digita le data) over several lines (bus lines) to the transmitted to various ICs by a bus logic of the ICs evaluated and the desired control function of the ICs running (for example a change in sound Strength).

Nowadays there are mainly two such bus systems common: the three-wire bus system (Japan, long-distance East), where the microprocessor with the connected ICs via a data, clock and enable line connected as well as the two-wire bus system (Europe, USA), where the microprocessor with the connected ICs connected via a data and clock line is. Integrated circuits in both bus systems can be used, the (otherwise functional same) ICs with the respective required under different bus logic can be equipped; from here right however, results in a double development effort work, on production costs, for warehousing etc.

It is an object of the invention to provide a simple circuit arrangement for the bus logic of an integrated switch  to specify the circle that the use of the same inte circuit in either two-wire bussy systems and three-wire bus systems.

This object is achieved by the features solved in the characterizing part of patent claim I.

Advantageous further developments of the invention result from the subclaims.

As can be seen from the block diagram shown in FIG. 1, the circuit arrangement of the "universal bus logic" has both a three-wire bus logic component 2 connected to three input lines 10 , 11 , 12 and one with the three input lines 10 , 11 , 12 connected two-wire bus logic part 1 . The data output D _OUT1 and D _{OUT2 of} the two bus logic parts 1 and 2 is via the data lines 15 and 16 with the data input D _IN31 and D _{IN32 of} the switching element 3 and the control _output S _OUT1 and S _OUT2 via the control line 13 or 14 connected to the control input S _IN31 or S _{IN32 of} the switching _element 3 (the switching process of the switching element 3 is initiated via the control lines 13 , 14 ). The data output D _{OUT3 of} the switching _element 3 is connected via the data lines 19 to the data input D _{IN4 of} the memory _element 4 , which is used to store the transmitted data DAT. The takeover _output Ü _OUT1 and Ü _{OUT2 of} the two-wire bus logic part 1 and the three-wire bus logic part 2 is ver via the control line 17 and 18 and a logic gate 5 with the charging input L _{IN of} the memory element 4 bound; the storage process in the memory element 4 is initiated by the bus logic parts 1 , 2 by a takeover pulse on the control lines 17 , 18 . At the data output D _{OUT of} the memory element 4 , the data DAT are transmitted on the data lines 20 to the various connected IC function units 6 . The output TM _{OUT of} the three-wire bus logic part 2 is connected via the switch 8 and the connecting line 21 to the test mode input TM _{IN of} the test mode unit 7 as part of the IC functional units 6 . This connection deactivates test mode unit 7 in three-wire bus mode (with switch 8 closed); by opening the switch 8 - the switch position is controlled via the signal level on the third input line device 12 - the deactivation of the test mode unit 7 can be prevented and thus the performance of function tests can be made possible (the opening of the switch 8 is made by applying a potential to earth potential) increased low level - e.g. 0.5 × V _S - initiated on the input line 12 ).

ICs with such a circuit arrangement can be connected as participants to both the three-wire bus system and the two-wire bus system: on the basis of the signals transmitted on the first input line 10 and the second input line 11 , the signal for the present data transmission ( Two-wire data transmission or three-wire data transmission) automatically activated suitable bus logic part 1 or 2 . Both bus logic parts 1 , 2 use the first input line 10 as a data line and the second input line 11 as a clock line; the third input line 12 has a double function: a constant voltage level (for example 0 V, supply voltage V _S , 0.5 × V _S ) is used to select the IC address in the case of two-wire data transmission, a voltage level change (low-high-low Jump) on this input line 12 acts as an activation signal or data transfer signal for three-wire data transmission; if the IC address for the two-wire data transmission is fixed, the two-wire bus logic part 1 only needs to be connected to the two input lines 10 , 11 .

The circuit arrangement according to the invention combines meh more advantages in itself:

• - Since the IC now for both bus systems at the same time can be used, the user has the free Choice of which bus system he wants to use; it can alternating both bus systems in one device operated in parallel (mixed assembly),
• - Manufacturers and customers need for both users cases (two-wire data transmission / three-wire Wire data transmission) only one IC and can thus extremely flexible to changes in the market react,
• - by sharing the three Buslei The IC requires solutions for both bus logic parts no additional connection pins,
• - The different bus logic parts can be common same bus logic unit.

In the Figs. 2 and 3, the timing diagrams for the case of two-wire data transmission (Fig. 2) and the three-wire data transmission (Fig. 3a, Fig. 3b) is Darge.

As can be seen from the timing diagram in FIG. 2, a high / low edge on the data line 10 is used according to the two-wire bus protocol as a starting condition for data transmission during the high phase of the clock signal CL on the clock line 11 (Time t₁) given. This is checked by the two-wire bus logic part 1 , which is activated when this start condition is present. When the bus address set on the third input line 12 by a constant voltage level, a data transmission to the IC functional units 6 is carried out. At time t 2, the data transmission is ended by sending a stop condition (low / high edge on the data line 10 during the high phase of the clock signal CL on the clock line 11 ).

In the case of data transmission without a start condition, the corresponding three-wire bus logic part 2 is activated, where different three-wire bus protocols can be processed: for example, the enable signal EN for data transfer on the third input line 12 is according to the timing diagram of FIG Fig. 3a be already output at the beginning of data transmission (low / high edge at time t₃), according to the timing diagram of FIG. 3b, however, only at the end of the data transmission (pulse at time t₄). However, in the three-wire bus protocol ( Fig. 3a, Fig. 3b) during the high phase of the clock signal CL on the clock line 11 no data changes (edge change on the data line device 10 ) are permitted; As a result, transmissions of three-wire bus protocols cannot be misinterpreted as two-wire bus data.

Claims (8)

1. Circuit arrangement for the bus logic of an integrated circuit, with:

• a) at least one three-wire bus logic part ( 2 ) connected to three input lines ( 10 , 11 , 12 ),
• b) at least one two-wire bus logic part ( 1 ) connected to at least two ( 10, 11 ) of the three input lines ( 10 , 11 , 12 ),
• c) a switching _element ( 3 ), the data inputs (D _IN31 , D _IN32 ) of which each have a data output (D _OUT1 , D _OUT2 ) of the bus logic parts ( 1 , 2 ) via data lines ( 15 , 16 ) and their control inputs (S _IN31 , S _IN32 ) are each connected to a control _output (S _OUT1 , S _OUT2 ) of the bus logic parts ( 1 , 2 ) via control lines ( 13 , 14 ),
• d) a memory _element ( 4 ), the data input (D _IN4 ) with the data output (D _OUT3 ) of the switching element ( 3 ) via data lines ( 19 ) and the charging input (L _IN ), each with a takeover _output (Ü _OUT1 , Ü _OUT2 ) the bus logic parts ( 1 , 2 ) is connected via control lines ( 17 , 18 ), and its data output (D _OUT4 ) _controls the functional units ( 6 ) of the integrated circuit via data lines ( 20 ).

2. Circuit arrangement according to claim 1, characterized in that the first input line ( 10 ) is the data line for transmitting the data (DAT) and the second input line ( 11 ) is the clock line for transmitting the clock signal (CL). 3. Circuit arrangement according to claim 1 or 2, characterized in that the two bus logic parts ( 1 , 2 ) are each connected to three input lines ( 10 , 11 , 12 ), the third input line ( 12 ) for selection of the bus logic part ( 1 or 2 ) has different voltage levels. 4. A circuit arrangement according to claim 3, characterized in that a constant voltage level on the third input line (12) the address of the two-wire Buslogikteils is adjustable (1), and that about level changes on the third input line (12) of the three Wire bus logic part ( 2 ) can be activated. 5. Circuit arrangement according to claim 1 or 2, characterized in that the two-wire bus logic part ( 1 ) is connected to two input lines ( 10 , 11 ), and that the address of the IC functional units ( 6 ) is fixed ben. 6. Circuit arrangement according to one of claims 1 to 5, characterized in that the bus logic parts ( 1 , 2 ) are designed as uniform circuit components. 7. Circuit arrangement according to one of claims 1 to 6, characterized in that when the three-wire bus logic part ( 2 ) is activated, the test mode unit ( 7 ) via the closed switch ( 8 ) by a signal at the test mode output (TM _OUT ) of the three -Wire bus logic part ( 2 ) can be deactivated. 8. Circuit arrangement according to claim 7, characterized in that the deactivation of the test mode unit ( 7 ) can be prevented by opening the switch ( 8 ) by means of an increased low level on the third input line ( 12 ).