DE4390098C2 - Liquid crystal display device - Google Patents

Description

Technical field

The present invention relates to a liquid crystal display device as used in a liquid crystal television det. In the present invention, a Character display method in a liquid crystal viewfinder portable video camera recording device (below video camera) improved by digitizing video signals. also the character display procedure is related to the steps of the Digitization of the video signals and their storage in one Memory in the steps of a special playback verbes like an auxiliary playback, a review playback and a still playback. Furthermore, when the video signal is digitized, pseudo vertical synchronis Sier signals caused by noise that with egg nem vertical sync signal are mixed, and also Flashes are due to a change in current Tension caused by the pseudo vertical synchro nisier signals is caused. The present invention aims depends on reducing the flashing process so that it is possible is to improve the quality of the ad.  

Underlying technology

Recently became a portable and compact liquid crystal TV with a liquid crystal display according to the Development of liquid crystal technology widespread. Furthermore be there are portable video cameras with liquid crystal images seekers in broad use for consumer applications that industrial application, etc., see e.g. B. the in the patent document US 5,164,834 disclosed video camera. One for control of liquid crystal displays providing the necessary clock or synchronization signals suitable scarf The device arrangement is described in US Pat. No. 4,393,405 ben. It is known to be in such liquid crystal displays directions the insertion of signs, symbols and the like in to provide the normal image to be displayed, see e.g. B. the Of Application EP 0 416 550 A2.

In general, the fade in position of the characters in the Display on a character display in the liquid crystal image viewfinder of the liquid crystal video camera through the synchronizer signal determined that was separated from the video signal. The Displaying various character information is common performed in the period of image acquisition in which the timing of the synchronization signal is regulated.

The reason that the character display is only in the period of Image acquisition is carried out in that the insertions of the characters because the synchronization signals are caused by noise be disturbed in the special reproduction, as in the auxiliary  playback, the review playback, the idle how and the playback including many noises Except for image capture and normal playback difficult becomes.

On the other hand, when using a current technology the type of video camera that ver digitized video signals applies such as the portable video camera with the liquid crystal Image viewer, the various character information as one Time display and a tape running display on the viewfinder Synchronization of the character display with the clock signal of the Liquid display can be displayed.

With this method of synchronizing the character display with however, the clock signal of the liquid display occurs during maximum  a clock interval an error because the video signal through the use of a reference clock of a control circuit the liquid crystal display device synchronously separated and that received video signal is digitized. Accordingly, there occurs the video signal with the character information as a time show up using the digitized clock signal is taken, a phase shift, i. H. a tremor during a maximum of one clock interval.

Furthermore, the liquid crystal viewfinder is usually used Video camera a shift in the time of generation Synchronizing signal that occurs immediately when the Rau during the switching time of the rotary head in the special Playback occurs when processed as a reset signal, and regardless of the amount of the shift, so that the front is started again for a horizontal direction. That is, that in the liquid crystal viewfinder of the portable video camera that has a so-called first-in-first-out memory (i.e. a FIFO memory) used, a shift of the generation the timing of the synchronization signal, which then immediately on occurs when the noise at the switching time of the rotary head in the special playback occurs, processed as a reset signal regardless of the amount of the shift, so that the reset process before completing the on write operation for a horizontal line in the FIFO memory cher is carried out.

In the above procedure, since the facility is straight as one Position works in which the reset process is carried out which is just the left end of the normal picture, ver all data after this position in the horizontal direction pushed so that the picture positions where noises turned on are mixed, also be moved horizontally. By doing For example, at the above stage, the sounds are twofold the ad mixed in and double shifts occur also on the picture according to the noise. To this  To solve the problem, the display is carried out in such a way leads to the first horizontal synchronizing signal into which the position is shifted, ignored and the characters on show is synchronized with the next synchronization signal.

Furthermore, once the characters appear on the liquid crystal image finder using the above type, the horizontal Sync signal ignored, displayed, the problem on that the character positions ent in the vertical position speaking of the number of horizontal synchronis ignored signals are shifted. As explained below, it will displayed image the shortened image in the vertical direction, because the horizontal synchronization signal is ignored. That is, it The following problems occur that the position of the time that are actually displayed in one direction above according to the number of ignored horizontal syn chronological signals is shifted, and there is an area in the under most area of the display where the image does not exist is.

Furthermore, the pseudo vertical synchronization signal is still at a conventional liquid crystal viewfinder, which is due to a faulty operation caused by noises in the special Playback in the synchronous separation circuit is caused on occurs as a reset signal in a scanning electrode drive circuit processed. As a result, a scanning electrode selected for the new vertical direction. On the other There are two methods for operating the scanning electrode the drive circuit of the liquid crystal display unit, so soon the vertical sync signal in one to the previous one Position different position is entered. That is, the The first method follows the scanning electrode signal, which was previously in the vertical direction has been selected and generates the scan electrode signal. The second method stops generating the Scanning electrode signal in the course of a control process in  the vertical direction, and starts the new control process for the scanning electrode.

There are two selection intervals for the first display method in the field because the method is the scanning electrode selection signal follows that to produce this signal previously in the verti direction worked. In this case, a effective tension compared to a normal level in which a selection interval exists in a field, and the Permeability of the liquid crystal is in the field interval increased, in which there are two selection intervals. As a result A flash occurs on the display where the picture becomes bright for a moment.

With the second display method, the effective voltage of the Liquid crystal display unit lowered in position after generation of the scanning electrode selection signal stopped since the method of generating the scanning electrode signal stops in the course of the control process in the vertical direction and starts driving in the vertical direction, and the flash process, in which the picture is bright for a moment appears on the display.

Disclosure of the invention

The first object of the present invention is to provide a syn to create a chronological method of a character display in which the Character information without phase shift and shivering into it Video signal can be displayed in normal playback, and various information during special playback can be displayed. The second task of the present Invention is to provide a display method that the Aus can prevent the number of image lines and the ver can switch off the display of characters. The third up The present invention is a display method  of a liquid crystal television to create the flash before can turn off the image on the display.

A liquid crystal display device according to claim 1 is used to achieve this object.

As one embodiment, the clock signal generation unit includes an A / D converter for receiving the video signal and its transformation into digital value; a pattern comparison circuit for receiving a synchronization signal and to perform the pattern matching process. One Synchronizing signal generating circuit for generating the clock signal in accordance with the pattern matching process; and a first-in-first-out memory (FIFO memory) for temporary registration of the digitized video signal and for reading it in accordance with the clock signal and a system clock.  

As a further embodiment, the clock signal generator includes supply unit for temporary storage Buffering the synchronization signal; a self-excited th counter for counting a write-in clock of the FIFO memory chers, for outputting an enable signal at a predetermined th count value, and for outputting a self-resetting sig nales to the latch circuit; an AND gate for Execution of the AND link between the output of the Zwi memory circuit and the enable signal, and for off give the reset signal to the self-excited counter switch circle; and a first-in-first-out memory for temporary use Storing the video signal in accordance with that by the Release signal or the reset signal controlled read and Registered operation.

As a further embodiment, the clock signal generator includes a field memory for temporarily storing the Video signal; a first control circuit for receiving the Synchronization signal, and for generating a first control signal nals for field storage; and a second control circuit to start based on a predetermined start signal and Generating the second and third control signals; being the Period for writing the video signal into the field memory due to the first control signal asynchronous with the period to Read the data from the field memory due to the second Control signal and to display the read data in the river Sig crystal display unit due to the third control signal is.

As a further embodiment, the first includes tax circuit a horizontal-vertical synchronization signal separation circuit for separating the synchronization signal into the horizontal synchronization signal and the vertical synchronization signal; a horizontal synchronizing signal counter circle for counting the horizontal synchronizing signal; one Enroll clock circuit for generating an enroll  clock in accordance with the count of the horizontal Synchronizing signal counter circuit; and a release signal nal generating circuit for generating the release signal in Agreement with the count; the expenditure of the A write clock circuit and the enable signal generator supply circuit in the field memory as the first control signal can be entered.

As a further embodiment, the second control switch includes circle: a counter circuit for counting the clocks of the system clock; a read enable generation circuit for off give the second control signal to the field memory in accordance matching the counter value of the counter circuit; and one Control signal generating circuit for the liquid crystal Show unit for outputting the third control signal to the Liquid crystal display unit in accordance with the count value.

Brief description of the drawings

Fig. 1 is a basic block diagram of a liquid crystal display device according to the present invention;

Fig. 2 is a signal pulse map for image acquisition and normal reproduction in the arrangement of Fig. 1;

Fig. 3 is a signal pulse overview for the special re delivery in the arrangement of FIG. 1;

Fig. 4 is a circuit diagram for a gate circuit and a delay circuit in the arrangement of Fig. 1;

Fig. 5 is a detailed block diagram of a clock signal generating circuit in the arrangement of Fig. 1;

Fig. 6 is another basic structural view of a clock signal generating circuit in the arrangement of Fig. 1;

Fig. 7 is an explanatory view of a display image for special reproduction according to the present invention;

Fig. 8 is an explanatory view of the display picture for normal reproduction;

Fig. 9 is an explanatory view of the display image of the special reproduction reset operation;

Fig. 10 is an explanatory view of the display image in which the dropout areas of the image line are shortened in the special display;

Figure 11a is a timing chart for normal operation;

Fig. 11b is a timing chart which explains a malfunction when noises are mixed in in the horizontal direction;

Fig. 12 is another block diagram for the clock generator circuit of the arrangement of Fig. 1;

Fig. 13 is a detailed block diagram of the first and second control circuits in the arrangement of Fig. 12;

Fig. 14 is a block diagram of a conventional technique corresponding to the arrangement of Fig. 12;

Fig. 15 is a timing chart explaining a flash caused by a pseudo vertical synchronizing signal; and

Fig. 16 is an explanatory view of a pseudo vertical synchronizing signal.

Best way to carry out the invention

An embodiment of the present invention will be explained with reference to the following drawings. Fig. 1 is a basic block diagram of a liquid crystal display device according to the present invention. Fig. 2 is a Sig nalimpuls overview for image recording and normal reproduction in the arrangement of Fig. 1. Fig. 3 is a Signalim pulse overview for the special reproduction of the arrangement of Fig. 1. Fig. 4 is a circuit diagram of a gate circuit and a delay circuit in the arrangement of FIG. 1st

In Fig. 1, reference numeral 101 denotes a video camera, 102 denotes a clock signal generating circuit, 103 denotes a synchronizing separation circuit, 104 denotes a first gate circuit, 105 denotes a delay circuit, 106 denotes a second gate circuit, and 107 denotes a liquid crystal display unit. The video signal VD of the video camera 101 is input to the clock signal generating circuit 102 and the synchronizing separation circuit 103 , and a synchronizing signal SY is output from the synchronizing separating circuit 103 . On the other hand, as soon as the clock signal generating circuit 102 receives the synchronizing signal SY, it outputs a clock signal TM, which is based as a kind of control signals on the synchronizing signal SY appearing on the liquid crystal display unit 107 , to the second gate circuit 106 , for example, one OR circuit.

The clock signal TM is controlled by the clock generation circuit 102 so that it receives the same period and pulse duration as the clocking of the synchronizing signal SY. In this case, the slight delay caused by circuit elements occurs, as shown by the synchronizing signal SY and the clock signal TM in FIG. 2. In the clock signal generating circuit 102 , a structure covering process is performed. For example, if the sync signal SY fails in the special reproduction, the clock signal TM is generated by a self-excited counter provided in the clock signal generating circuit 102 , and is continuously output and controlled in the constant interval to supply signals caused by mixed noise eliminate. In order to use the switching time of the synchronizing signal SY when the clock signal TM is output, the AND operation between the synchronizing signal SY and the clock signal TM is carried out in the first gate circuit 104 , for example the AND circuit, and the output AO is carried out during of the AND operation in the delay circuit 105 .

The delay circuit 106 delays the AND output AO to bypass the switch position of the clock signal TM and outputs the delay signal DL to the second gate circuit 106 . The second gate circuit 106 generates the sync signal CSY for the character display in accordance with the clock signal TM and the delay signal DL, and outputs it to the video camera 101 . In the present invention, character signals are generated based on the timing of a trailing edge of the synchronization signal CSY for the character display.

In Fig. 2, the synchronizing signal SY is the signal that is output by the synchronizing separation circuit and is based on the video signal VD, the clock signal TM is the signal that is output by the clock generating circuit, the AND output AO is the signal that by the AND circuit is output and based on the AND operation between the synchronizing signal SY and the clock signal TM, the delay signal DL is the signal which is delayed by the AND output AO, and the synchronizing signal CSY for the character display is the signal which is the output based on the delay signal DL and the clock signal TM. The synchronizing signal CSY for the character display is input to the video camera and is used as the synchronizing signal for the character display. In the drawing, the front and back circled areas show the switching timing of various signals, and the arrows in the drawing show that the timing of the origin of the arrow produces the timing of the tip of the arrow.

In Fig. 3, each signal corresponds to the signal shown in Fig. 2. In this example, the synchronization signal SY has failed as shown in the drawing. Since the timing of the synchronization signal does not change, the AND output AO and the delay signal DL are not shown in the drawing. The clock signal TM of the clock generating circuit is input to the OR circuit and generates the synchronizing signal CSY for the character display.

In Fig. 4, the AND circuit 111 corresponds to the first gate circuit 104 and is made up of resistors and capacitors. The delay circuit 112 corresponds to the delay circuit 105 , and the NOR circuit 113 corresponds to the second gate circuit 106 . The converter 114 is provided for transforming the output of the NOR circuit and is constructed from the OR circuit in which the NOR circuit is included. Furthermore, IN1 denotes an input terminal of the synchronization signal SY, IN2 denotes an input terminal for the clock signal TM, and OU1 denotes an output terminal for the synchronization signal of the character display. The explanation of the NOR circuit and the OR circuit is omitted because these circuits are well known.

Fig. 5 is a detailed block diagram of the clock signal generating circuit in the arrangement of Fig. 1. As shown in the drawing, the video signal VD is converted into the digital signal by the A / D converter 102 a, and the digital signal stored in the FIFO memory 102 e. On the other hand, a synchronizing signal is generated in the Syn chronisiertrennschaltkreis 103 based on the video signal type b incorporated in the pattern comparison circuit 102, and is used as a synchronizing signal b for the known pattern matching circuit 102nd The output of the pattern comparison circuit 102 b is input to the synchronizing signal generation circuit 102 c and generates the clock signal TM. Furthermore, the output of the synchronizing signal generating circuit 102 c is input to the memory control circuit 102 d and controls the writing into and reading from the FIFO memory 102 e. The system clock 102 f generates a clock that controls the operation of these circuits.

According to the first aspect of the present invention it is possible to pre-synchronize a character display watch at the character information that no phase distortion and have no flickering in the video signal at nor painterly playback can be shown and various In information during special playback can.

An embodiment of another aspect of the vorlie invention is explained with reference to the drawings. Fig. 6 is another basic structural view of a clock signal generating circuit of the arrangement of Fig. 1, Fig. 7 is an explanatory view of a display image during special playback according to the present invention, Fig. 8 is an explanatory view of the display image during normal Playback, Fig. 9 is an explanatory view of the display image in the reset operation of the special reproduction, and Fig. 10 is an explanatory view of the display image in which the dropout areas of the image lines are reduced during the special reproduction.

In Fig. 6, the synchronizing signal SY obtained by the video signal VD is input to the latch circuit 121 . A once latched signal is input to gate circuit 122 . The self-excited counter 123 counts the write-in clocks of the FIFO memory 124 and generates the self-resetting signal SR at a predetermined count value. The self-resetting signal SR is in addition to the input to the latch circuit 121 . In this case, the self-resetting signal SR corresponds to the clock signal TM from FIG. 4.

If the write operation is not performed in the FIFO memory 124 which receives the video signal VD, the output of the gate circuit 122 operates as a reset signal RS of the self-excited counter 123 , so that the self-excited counter 123 is reset, and the latch circuit 121 is also reset. YES / NO (executed / not executed) of the writing operation in the FIFO memory 124 is controlled in accordance with the enable signal WE of the self-excited counter 123 .

During the writing process in the FIFO memory 124 , in which the synchronization signal SY is input into the buffer circuit 121 , YES / NO (present / not present) the input of the synchronization signal is stored and held in the buffer circuit 121 . Since the gate circuit 122 is separated based on the enable signal WE to the FIFO memory 124 , the reset signal from the gate circuit 122 is not input to the self-excited counter 123 . Since the output of the enable signal WE from the self-excited counter 123 to the FIFO memory 124 continues, the FIFO memory 124 accordingly continues the write process of the video signal.

As soon as the writing process into the FIFO memory 124 has ended completely, the gate circuit 122 is connected by the release signal WE. Once the synchronizing signal SY, which is held in the latch circuit 121, is input to the Gat terschaltkreis 122, the gate switching sends the reset signal RS to the self-excited counter 123 circular 122nd The self-excited counter 123 is reset by the reset signal. As a result, all of the above processes can be continued at the stage that the synchronizing signal is not ignored.

On the other hand, in the reading operation of the FIFO memory 124, the data corresponding to the number of picture elements within a horizontal period is read by the FIFO memory 124 , regardless of YES / NO of the pseudo-synchronizing signals caused by noises and in an optional timing within a horizontal period. The data is displayed on the liquid crystal display unit. In this case, the arrangement of the data in the FIFO memory 124 corresponds to the arrangement of the data displayed on the liquid crystal display unit.

Based on the above control, the image that appears immediately after noise appears in the special reproduction is shifted in accordance with the amount of shift in the position in which the horizontal synchronizing signal exists. However, this shift is gradually corrected and returned to the original position. At this time, the shift in the vertical direction, as shown in Fig. 7, has not occurred because the horizontal synchronizing signal is not skipped. In addition, since the write operation to the FIFO memory 124 was not interrupted, the shift in the horizontal direction is not continued, so that it is possible to change the normal position of the character display without the display, which is shortened in the vertical direction shown in FIG. 10.

In Fig. 9, the shift in the liquid crystal view finder of the video camera using the FIFO memory is also shown. In this case, the resetting operation is started from the shifted position of the synchronizing signal immediately after the occurrence of noise in the switching timing of the rotary head in the special reproduction, such as the auxiliary reproduction, the verification reproduction and the still reproduction.

The explanation will be given as follows with reference to Fig. 10: The horizontal synchronizing signal to which the generating position is shifted is passed at a stage shortly after the noise in the switching timing of the rotary head has occurred in the special reproduction . Accordingly, the display is carried out by synchronizing with the next synchronizing signal. Fig. 11a shows a pulse map in normal operation, and Fig. 11b shows a pulse map explaining an erroneous operation in which noise is mixed in the horizontal direction. This pulse overview characterizes the relationship of the signal timing between the video signal VD, which is input to the synchronizing separation circuit 103 in FIG. 1, the synchronizing signal SY, which is created by the synchronizing separating circuit 103 based on the video signal VD, and the release signal WE (see Fig. 6) which performs control to store the video signal VD in the FIFO memory 124.

In the drawing, the video signal VD is the video signal in normal operation, and the synchronizing signal SY is generated based on the video signal. As shown in Fig. 1, the synchronizing signal SY is input to the clock signal generating circuit 102 so that the control signal CS1 is generated as a release signal of the field memory 131 .

Fig. 11b further shows the disturbance of the synchronizing signal SY, if noise during special playback are mixed. The pulse shape of the video signal VD in the special reproduction is completely different from the reproduction which contains noise. However, since the synchronizing signal, the enable signal and the occurrence of the erroneous operation are given by the same explanations as above, only noises mixed in the signal are shown in these drawings. Once the noise is mixed in, the sync signal SY exists and the pseudo sync signal PSY is generated as shown by the circles in Fig. 11b. For noises in the special replay, the synchronization signal does not exist, and only the pseudo synchronization signal PSY is generated. In both abnormal cases, the interval between the synchronizing signals is not constant, as shown in the drawing.

To simplify the explanation, the video signal VD is turned off nine dates formed. In addition, the synchronization signal represented by "S", the pseudo sync signal represented by "P", the area where the character is not is present, is expressed by "0", continuous signals are represented by ten digits "0" to "9". The video sig nal VD in normal operation can be "S0123456789, S0123456789, . . . "are expressed. Since the areas" 0 "in which the time Chen does not exist, deleted by the release signal the video signals are stored in the memory in the form of "123456789, 123456789,..." Stored. These data trains are displayed on the liquid crystal unit consisting of nine Elements is formed as follows.

It is assumed that an impulse of noise into the Facility is entered. The video signal VD becomes  "S0123456789, S1234P6789, S123456789, ...". As stated above the data trains "123456789, 1234-6789, 123456789,..." in stored in the memory since the synchronization signal S and area 0, in which the data does not exist, is deleted will. Similarly, the data trains, the nine data have indicated on the liquid crystal display unit as follows shows.

As is clear from the above, the information becomes "1" which is on the left side should be shown by the noise, that was mixed in, shifted to the right side.

According to the present invention, the scanning operation on the Memory done for the horizontal direction until nine Data is complete when the pseudo sync signals are mixed in. As a result, the data shift occurs not in the present invention. Once the videotape expanded or the channel was changed, the normal Synchronizing signal shifted so that it is necessary to Recording of the synchronization signal within the scanning sig stopping.

It is assumed that the video signals pass through the train "S0123456789, S0123P0000, S0123456789, S012345678,..." be put.

In the known prior art, the data trains "123456789, 1230000, 123456789, 123456789, 123456789" in the Memory saved and displayed as follows.  

In the present invention, the data trains "123456789, 123P00P00, S0123456789, S0123456789, S0123456789,. . . " by doing Memory saved and displayed as follows.

As can be seen from the above data flow, it regenerates Data train soon after the noise is mixed in. Whether probably the current liquid crystal six hundred and forty pixels has elements in the horizontal direction, is on the Er refined, because for this large number of picture elements same explanation would be given.

As explained above, it is according to the second Ge point of view of the present invention possible a liquid crystal viewfinder to realize the failure of picture can prevent and shift the position of the lines Can exclude character display.

The third aspect of the present invention will be explained with reference to the drawings. Fig. 12 is a block diagram according to an embodiment of the third aspect punk tes of the present invention. In Fig. 12, 131 denotes a field memory that corresponds to the FIFO memory. Furthermore, the first control circuit 132 and the second control circuit 133 are integrated in the clock generation circuit explained above. The video signal VD is input to the field memory 131 in accordance with the control signal CS1 output from the first control circuit 132 controlled by the synchronizing signal SY. On the other hand, the second control circuit 133 is started due to the power on and driven asynchronously to the first control circuit 132 . The second control circuit 133 also outputs the control signal CS2 to the field memory 131 , and reads the contents of the field memory in accordance with the read period regardless of the write period. The video information VDA is sent from the field memory to the liquid crystal display unit 107 . In this case, the video information VDA is synchronized with the control signal CS3 of the second control circuit 133 .

Fig. 13 is a detailed block diagram of the first and second control circuits of Fig. 12. In the first control circuit 132 , the synchronizing signal SY in the horizontal-vertical synchronizing signal separation circuit 132 a enter, and the horizontal-vertical synchronizing signal separation circuit 132 a outputs the horizontal synchronizing signal HSY and the vertical synchronizing signal VSY to the horizontal synchronizing signal counter circuit 132 b. An output of the horizontal Synchronisiersignalzählschaltkreises 132 is sent c to the enable signal generation circuit 132 b, the other output is sent to the write pulse generating circuit 132 d. Both outputs of the enable signal generation circuit 132 c and the write-in clock generation circuit 132 d are sent to the field memory 131 as a control signal CS1 based on the clock pulse SC from the system clock 102 f. The field memory 131 receives the video signal VD.

In addition, in the second control circuit 133 of the system clock SC to the counter circuit 133 a entered. The counted value of the counter circuit 133 a is entered into the read release generation circuit 133 b, and also with the output from the read release generation circuit 133 b as a control signal CS2 entered in the field memory 131 . Furthermore, the counted value of the counter circuit 133 a in the control signal generating circuit 133 of the integrated input Flüssigkristallanzeigeein c, and the output of the control signal generating circuit 133, c is input to the liquid crystal display unit 107 as a control signal CS3. Furthermore, the read information DA from the field memory 131 is input to the liquid crystal display unit 107 based on the control signal CS3.

Fig. 14 is a block diagram of a conventional construction corresponding to Fig. 12. As shown in Figs. 12 and 14, the video signal VD is input to the field memory 131 based on the control signal CS4, which was output from the control circuit 134 , which is controlled by the synchronizing signal SY and is read depending on the read period having a period which is synchronous with the write period of the field memory 131 . In addition, the video signal is sent to the liquid crystal display unit 107 , which is controlled by the control signal CS5 of the control circuit 134 . The control signal CS5 is synchronized with the synchronizing signal and the video information VDA, which was read from the field memory 131 .

In the above arrangement, the synchronizing separation circuit 103 operates in accordance with the video signal having a noise and a noise that occurs in the switching timing of the rotary head in the special reproduction of the video cassette recorder, so that a pseudo vertical synchronizing signal PSY is generated as soon as the vertical Synchronization signal is given. As described below, the reset signal RS of the scanning electron drive circuit (not shown) is generated by the control circuit 134 to the field memory 131 as soon as the pseudo vertical synchronization signal PSY is input to the control circuit 134 as the synchronization signal SY. The write-in address of the field memory 131 is reset by the reset signal RS, and the write-in process is started from the start area of the field memory. Since the display timing of the liquid crystal display unit 107 is synchronized with the synchronizer signal SY, the display timing is reset due to the input of the pseudo synchro signal PSY.

In fact, since the display clock of the liquid crystal with the timing of the synchronization signal SY is synchronized, this synchronization in the case of vertical synchronization Siersignals effective that at a different position than at the original position is entered, and in the event of Display of the video signal showing the fluctuation of the field period has that in the special playback of a video cassette recorder occurs.

On the other hand, in the circuit of the present invention, as shown in FIG. 12, the synchronizing separation circuit fails due to the noise that occurs in the switching timing of the rotary head in the special reproduction. As a result, the pseudo vertical synchronization signal is generated as soon as the vertical synchronization signal is entered.

Once the pseudo vertical synchronizing signal is input to the first control circuit as the synchronizing signal SY, the reset signal of the scanning electrode drive circuit (not shown) is generated by the first control circuit, the write address of the field memory 133 is reset, and the write operation is started from the beginning area of the memory .

However, since the control signal CS2 for the reading clock of the field memory is generated by the second control circuit 133 asynchronously with the control signal CS1 of the first control circuit 132 , the display period of the liquid crystal display unit remains constant regardless of the write-in period of the field memory, so that an effective voltage is not changes.

Since the repetition period of the display in the liquid crystal stall display unit the same period as that of Feldspei in this case, the repetition period will not synchronized with the video signal. As a result, the re display period in the liquid crystal display be set to the desired periods.

Disclosed in JP-A-1-233978 and JP-A-3-84502 the inventor of the present invention a liquid crystal pointing element having a liquid crystal having a Angle of rotation of more than 90 ° (i.e. a super twisted nemati liquid crystal) between a pair of circuit boards which has the scanning electrode and the signal electrode have opposite sides. It also reveals one Liquid crystal display device which takes advantage of the fact that the contrast in case of a double repetition period in the display unit becomes maximum when displaying method of the liquid crystal television that controls the control Circle for controlling the display elements.

The present invention sets the period as double and as a half, based on the above principle. In which Case of the liquid crystal display unit, the display period can not last longer than the period of the video signal the liquid crystal continues through the same process as the field period of the video signal are operated. In this In this case, the increase in the period is not defined.  

Fig. 15 is a timing chart for explaining the Blitzvor process caused by the pseudo vertical synchronizing signal. The present drawing shows the cause of the flashing process due to the pseudo synchronizing signals that occur due to the special reproduction and noises that are mixed in there. In the drawing, the vertical synchronizing signal VSY shows the signal in normal operation, and the pseudo vertical synchronizing signal PSY represents the output of the scanning electrode S1, S2, S3,. . . represents when the signal PSY is mixed during the interval T5. In the interval T5, the start signal is input to the scanning electrode control circuit depending on the pseudo synchronizing signal PSY, and drive pulses are output to the scanning electrode depending on the number of pseudosynchronizing signals PSY in the interval T5. As a result, the effective voltage supplied to the liquid crystal becomes higher in the interval of T5 compared to another period, so that it is possible to operate the liquid crystal. This is the cause of the flashing process.

Fig. 16 is an explanatory view of the pseudo vertical sync signal. Once the pseudo sync signal PSY is generated by the noise in the vertical sync signal, part of the video signal VD fails due to the noise, as shown by the dashed circle. The synchronizing separation circuit 103 , which inputs the video signal VD as soon as the signal is adapted to the conditions of the vertical synchronizing signal VSY, recognizes the signal as a vertical synchronizing signal so that the vertical synchronizing pulse is generated.

As explained above, it is possible to pseudosynchronize to prevent signal that due to malfunction of the syn chronizing isolating circuit occurs, which ver is caused, and the change in the effective voltage at Avoid resetting the scanning electrode drive circuit  the one caused by the pseudo vertical synchronization signal is gently because of the incorrect operation of the Syn chronizing circuit in the special reproduction of the Videocassette recorder occurs, and the flash operation ver prevent that by changing the effective tension was caused.

Applications for the industry

In the liquid crystal display device, as in a Liquid crystal television used improves the present invention the method of displaying characters in the river sig crystal viewfinder of the portable camera in which the video signal is digitized. In addition, the present improves Invention in the processes that digitize the video signal and store in a memory, the method of characters display in special playback, such as auxiliary playback and review playback. In addition, the present Invention reduce the flash process due to the Change in effective tension caused by the pseudo vertical synchronization signal caused by Noise is caused which is in the vertical sync signal is mixed in when the video signal is digitized becomes. As a result, it is possible to determine the quality of the characters show to improve. Accordingly, the present invention can widely used in various industries.

Claims (8)

1. A liquid crystal display device, characterized in that it has the following:
Clock signal generating means ( 102 ) receiving a video signal from a video camera ( 101 );
Synchronizing separation means ( 103 ) for generating a synchronizing signal (SY) based on the video signal;
first gate means ( 104 ) for receiving a clock signal (TM) from the clock signal generating means and the synchronizing signal, performing a logical product (AND operation) and outputting the result (AO) of the AND operation;
Delay means ( 105 ) for delaying the output signal of the first gate means by at least a time period corresponding to the delay of the clock signal with respect to the synchronizing signal;
second gate means ( 106 ) for receiving the clock signal and the delay signal (DL) from the delay means, performing a logical sum (OR operation) and outputting the result of the OR operation; and
a liquid crystal display unit ( 107 ) for receiving and displaying video information (VDA) from the clock signal generating means;
wherein the clock signal generating means perform a pattern comparison for the synchronization signal for detecting fluctuations in the same and generate the clock signal in accordance with the synchronization signal with compensation for any fluctuations thereof; and
the second gate means feed the clock signal or the delay signal back into the video camera in order to use it as a synchronous signal (CSY) for the character display. 2. A liquid crystal display device according to claim 1, wherein the clock signal generating means comprises: an A / D converter ( 102 a) for receiving the video signal and converting it into a digital value; a pattern comparison circuit ( 102 b) for receiving the synchronization signal and for performing the pattern comparison process; a synchronizing signal generating circuit ( 102 c) for generating the clock signal (TM) in dependence on the pattern comparison process; and a first-in-first-out memory (FIFO memory) ( 102 e) for temporarily writing in the digitized video signal and reading it in response to the clock signal and a system clock. 3. A liquid crystal display device according to claim 1, wherein the clock signal generating means includes: a latch circuit ( 121 ) for temporarily latching the synchronizing signal; a self-excited counter ( 123 ) for counting a write-in clock of the FIFO memory, for outputting an enable signal (WE) at a predetermined count value, and for outputting a self-resetting signal (SR) to the latch circuit; an AND gate ( 122 ) for performing the AND operation between the output of the latch circuit and the enable signal and for outputting the reset signal (RS) to the self-excited counter circuit; and a first-in-first-out memory ( 124 ) for temporarily storing the video signal (VD) in accordance with the read and write operation controlled by the enable signal or the reset signal. The liquid crystal display device according to claim 1, wherein the clock signal generating means includes: a field memory ( 131 ) for temporarily storing the video signal; a first control circuit ( 132 ) for receiving the synchron signal and for generating a first control signal (CS1) for the field memory; and a second control circuit for starting on the basis of a predetermined start signal (ST) and for generating the second and third control signals (CS2, CS3); wherein the period for writing the video signal into the field memory based on the first control signal is asynchronous with the period for reading the data from the field memory based on the second control signal and for displaying the read data in the liquid crystal display unit due to the third control signal. 5. A liquid crystal display device according to claim 4, wherein the first control circuit comprises: a horizontal-vertical synchronizing signal separating circuit ( 132 a) for separating the synchronizing signal into the horizontal synchronizing signal (HSY) and the vertical synchronizing signal (VSY); a horizontal synchronizing signal counting circuit ( 132 b) for counting the horizontal synchronizing signal; a write clock generating circuit ( 132 d) for generating a write clock depending on the count of the horizontal synchronizing signal counter circuit; and a release signal generating circuit ( 132 c) for generating the release signal in dependence on the count value; outputs of the write-in clock generation circuit and the enable signal generation circuit are input to the field memory as a first control signal. 6. A liquid crystal display device according to claim 4 or 5, wherein the second control circuit comprises: a counter circuit ( 133 a) for counting the clock (SC) of the system clock; a read enable generation circuit ( 133 b) for outputting the second control signal to the field memory in dependence on the count value of the counter circuit; and a control signal generating circuit ( 133 c) for the liquid crystal display unit for outputting the third control signal to the liquid crystal display unit depending on the count value. 7. Liquid crystal display device according to one of the claims 1 to 6 with a liquid crystal viewfinder, through a Clock signal is controlled using a fluctu ation-compensating pattern comparison process from the syn Chronsignal SY is obtained from the video signal VD one portable video camera separated by a compact turret , the clock signal being fed back into the video camera will and characters in the video signal in synchronization with the Clock signal are shown, characterized in that the switching timing of a level of the clock signal, which in the Video camera is fed back during an image capture and a normal reproduction on the switching timing of a delay tion signal is set by delaying the synchro is obtained before the pattern matching process, and that during a special playback, such as an auxiliary play, a review play, and a stand play sabe, on the switching timing of the clock signal according to the pattern comparison process is set.   8. Liquid crystal display device according to one of claims 1 to 6 with a liquid crystal viewfinder ( 107 ), in which a fluctuation-compensating pattern comparison process for the syn chronizing signal (SY) is carried out, which is separated from the video signal (VD) of the portable video camera with a compact rotary head, and the content of a memory ( 124 ) is displayed, which is controlled depending on a self-excited clock signal, the clock signal being fed back into the video camera and characters being inserted into the video signal in synchronization with the clock signal, characterized in that
the synchronization signal (SY) output from the video camera is subjected to the pattern comparison process; immediately after the noise in the switching timing of a rotary head of the video camera in a particular reproduction occurs, an existence / non-existence of a synchronizing clock signal (SY, TM) caused by a shift in the generation position of the synchronizing signal during a write operation is temporarily stored in the memory ( 121 );
the write to the memory ( 124 ), if the input of the synchronizing clock signal exists, is started immediately after the completion of the write to the memory ( 124 ); and the write to the memory is started based on the next clock signal when the input of the synchronizing clock signal does not exist.