DE4334633C1 - Method and circuit arrangement for evaluating stochastically occurring measured values - Google Patents

Abstract

The invention relates to a method and circuit arrangement for evaluating stochastically occurring measured values in a sequence of measured values with fast measurement rate. The object of the invention is hence to make the measured-value sequence evaluatable in a predetermined time interval before and after an event. This is achieved in that, according to the invention, the measured values are cyclically converted into digital values, cyclically input into a memory block and cyclically shifted forward, measured values deviating from the comparison value in the middle of the memory block are determined, the entire measured-value sequence associated with the deviating measured values is stored, date and time are established and the stored measured-value sequence is represented with the partial measurement sequence existing before and after the deviating measured value. <IMAGE>

Description

The invention relates to a method and a circuit order for evaluation of stochastically occurring analog, electrical measured values in a measured value series with faster Measurement sequence, according to the preambles of claims 1 and 2.

When evaluating measured values in a series of measured values with faster measurement sequence are especially for determining sto measurement values that appear chastically, also not of interest Measured values recorded, so that a considerable effort in the Registration and evaluation is required.

To reduce this effort, it is known from a A measurement-dependent selection of Measured values to meet (DE 25 42 597 A1) by only the Exceeding values in relation to a limit value constantly checked and registered.

However, the solution has the disadvantage that the measured values not before and after the exceeding value occurs be evaluated, although for a variety of event These measured values are of particular interest in order to draw conclusions se to cause.

DE 31 32 874 A1 provides an arrangement for the effective value measurements of voltage signals are announced, at which the sampled measured values converted in an A / D converter and their effective values are calculated in a computer become. The remarkable thing about this arrangement is that the Processing speed of the evaluation computer independent gig selected from the input signal frequency can be. This is achieved through a temporal stocha tical sampling of the input signal, which in a given A time grid takes place. However, this is for one rapid measurement signal sequence of the rms value with a computer not to be calculated because corresponding analog computing circuit can only be used for low-frequency measurement signals can.  

The cutoff frequency of the arrangement is determined only by the sampling circuit determined.

DD 2 23 830 A1 describes an arrangement which to reduce interference, especially noise, with periodic measurement signals. For elementary use A / D converter, a shift register and an input Storage. The special feature of this arrangement is one Averaging that excels with digital Circuit technology can be implemented. But that's about it Measurement signal cannot be researched, so that the cause of measurement deviations in value can no longer be detected.

The invention is therefore based on the object in one predefined time interval before and after an event To make a series of measured values evaluable.

This is achieved in that the analog Measured values are intermittently converted into digital values, clocked written in a block of memory and clockwise from memory cell to memory within the memory block cell to be pushed so that it is in the middle Memory element of the memory block measured value in a comparator is compared with a target value and in the event of a deviation from the nominal value, the deviating measurement whole series of measurements, represented by the content of the Memory blocks, as well as date and Time in another memory and the stored measured value series with the before and after the deviating measured value existing partial measurement series on a Screen is displayed. The task is also carried out by the in the features specified claim 2 solved. In claim 3 is a circuit arrangement for performing the method according to claim 2 specified. Advantageous refinements of the circuit arrangement according to the invention are specified in patent claims 4 and 5.

The invention will be explained in more detail using an exemplary embodiment explained. The accompanying drawing shows:

Fig. 1 shows the block diagram for evaluation with arranged in the shift register output signal,

Fig. 2 shows the block diagram for evaluation with the signal output arranged at the end of the shift register.

The measured value output 1 for the measured value series is connected to the input of the analog / digital converter 2 , the output of which is connected to the input of the shift register 3 and to the comparator 9 ( FIG. 1).

Analog / digital converter 2 and shift register 3 are coupled to the clock generator 4 . The shift register 3 has the output 5 and the measured value output 6 . The measured value output 6 is connected to the comparator 8 . The setpoint generator 7 is connected to comparator 8 and comparator 9 .

The output of the comparator 8 is connected to the control input 13 of the switch 12 , the input 14 of the switch 12 to the output 5 of the shift register 3 and the output 15 of the switch 12 to the input of the static memory 19 .

The output of the clock 10 is connected to the input 17 of the switch 11 , the output of the comparator 9 to the control input 16 of the switch 11 and the output 18 of the switch 11 to the static memory 19 .

The output of the static memory is connected to the display device 20 .

The mode of action is as follows:
The series of measured values at the measured value output 1 in the form of an analog signal is converted into digital values in the analog / digital converter 2 . The clock generator 4 provides the clock control for the analog / digital converter 2 and the shift register 3 .

The clock control determines the sampling frequency of the entire Arrangement.

The output of the analog / digital converter 2 is connected to the comparator 9 , so that the currently converted digital values are immediately compared with the setpoint, predetermined with the setpoint generator 7 .

In the event of a deviation from the nominal value, the comparator 9 outputs a corresponding signal which acts on the input 16 of the switch 11 in such a way that the time / date information 10 is switched from the input 17 to the output 18 of the switch 11 to the static memory 19 .

The clock-by-clock values present at the output of the analog / digital converter 2 are written into the shift register 3 , the 1st digital value being written in the 1st clock in the 1st storage element of the memory block, in the 2nd clock the content of the 1st Storage element (1st digital value) is written into the 2nd storage element and the 2nd digital value is read into the 1st storage element. The process continues until the 1st digital value appears in the last storage element, in the following cycle the content of the last storage element (1st digital value) is overwritten by the 2nd digital value and so on. In the memory block, the digital values "migrate" continuously from the first memory element to the last memory element. In this way, a time-shifted image of the measured value row present at measured value output 1 is created.

The shift register output 6 decouples the value of the middle storage element and passes it to the comparator 8 . This value is compared with the setpoint in setpoint generator 7 in each cycle. In the event of a deviation from the target value, a corresponding signal is given to input 13 of switch 12 .

This signal causes the entire content of the shift register 3 at the output 5 to be switched to the static memory 19 via the input 14 and output 15 of the switch 12 . This results in an image of the measured value series in the static memory, in the center of which is the deviating measured value, that is to say measured values before the deviating measured value and measured values after the deviating measured value. By selecting the number of memory elements in the memory block and the clock frequency, the time differences between the partial measured value series and resolution can be determined.

The measured value output 1 for the measured value series is connected to the input of the analog / digital converter 2 , the output of which is connected to the input of the shift register 3 and to the comparator 8 having the setpoint generator 7 ( FIG. 2). Analog / digital converter 2 and shift register 3 and counter 21 are coupled to the clock generator 4 .

The shift register 3 has the output 5 , which is connected to the input 14 of the switch 12 . The clock 10 is connected to the input 17 of the switch 11 . The control input 16 of the switch 11 is coupled to the output of the comparator 8 and to the control input of the counter 21 . The output 18 of the switch 11 is connected to the static memory 19 . The output 22 of the counter 8 is connected to the control input 13 of the switch 12 , the output 15 of the switch 12 to the static memory 19 . The output of the static memory 19 is coupled to the display device 20 .

The mode of action is as follows:
The series of measured values at the measured value output in the form of an analog signal is converted into digital values in the analog / digital converter 2 . The clock generator 4 provides the clock control for the analog / digital converter 2 and the shift register 3 .

The clock control determines the sampling frequency of the entire Arrangement.

The output of the analog / digital converter 2 is connected to the comparator 8 , so that the currently converted digital values are immediately compared with the setpoint, predetermined with the setpoint generator 7 .

In the event of a deviation from the target value, the comparator 8 outputs a corresponding signal, which acts on the control input 16 of the switch 11 in such a way that the time / date information 9 is switched from the input 17 to the output 18 of the switch 11 to the static memory 19 . At the same time, the counter 21 is started.

The clock-by-clock values present at the output of the analog / digital converter 2 are written into the shift register 3 , the 1st digital value being written into the 1st storage element in the 1st clock, the content of the 1st storage element in the 2nd clock (1st digital value) is written into the 2nd storage element and the 2nd digital value is read into the 1st storage element.

The process continues until the 1st digital value appears in the last storage element, in the following cycle the content of the last storage element (1st digital value) is overwritten by the 2nd digital value and so on. In the memory block, the digital values "migrate" continuously from the first memory element to the last memory element. In this way, a time-shifted image of the measured value row present at measured value output 1 is created.

The counter 21 counts as many clocks of the clock generator 4 as half the number of memory elements in the memory block 3 and then outputs to the screen 20 a corresponding signal which, via the control input 13 of the switch 12, switches the contents of the memory block 3 at the output 5 to the input 14 of the switch 12 to the output 15 of the switch 12 to the static memory 19 .

Thus, an image of the measured value series is formed in the static memory 19 , in the center of which is the deviating measured value, that is to say measured values before the deviating measured value and measured values after the deviating measured value. By selecting the number of memory elements in the memory block and the clock frequency, the time differences between the partial measured value series and resolution can be determined.

Reference list

1 measured value output
2 analog / digital converters
3 shift registers
4 clock generator
5 exit
6 measured value output
7 setpoint adjuster
8 comparators
9 comparators
10 a.m.
11 switches
12 switches
13 control input
14 entrance
15 exit
16 control input
17 entrance
18 exit
19 memory
20 screen
21 counters
22 exit

Claims (5)

1.Procedure for the evaluation of stochastically occurring analog, electrical measured values in a measured value series with a fast measuring sequence, the measured value series being checked for exceeding a limit value, characterized in that the analog measured values are converted into digital values in cycles, are written into a memory block 3 in cycles, and are cyclically within of the memory block (3) are pushed further from memory cell to memory cell that the measured value located is compared in a comparator (8) with a desired value in the central storage element of the memory block (3) and in case of deviation from the desired value, belonging to the deviating measurement entire series of measurements , represented by the content of the memory block ( 3 ), and the date and time are stored in a further memory ( 19 ) and the stored measurement value series with the partial measurement series existing before and after the deviating measurement value are shown on a screen ( 20 ) lt will. 2. A method for evaluating stochastically occurring analog, electrical measured values in a measured value series with a fast measurement sequence, the measured value series being checked for exceeding a limit value, characterized in that the cyclically digitized values are compared in a comparator ( 8 ) provided with a setpoint generator ( 7 ) and if the value deviates from the target value, a clock counter ( 21 ) is started, the counter reading of which, when a number is reached, which corresponds to half the number of memory elements of the memory block ( 3 ), the content of the entire memory block ( 3 ) and date and time at the time of the deviation of the value from the target value in a static memory ( 19 ), such that the stored measured value series with the partial measurement series consisting of before and after the deviating measured value is displayed on a screen ( 20 ). 3. Circuit arrangement for performing the method according to claim 1, characterized in that the output of the measured value series with a clock-controlled analog / digital converter ( 2 ) and at the output of a clock-controlled shift register ( 3 ) (dynamic memory) and the input of a a setpoint generator ( 7 ) provided first comparator ( 7 ) and the output of the comparator ( 9 ) is connected to a static memory ( 19 ), a memory cell with a signal output being arranged in the middle of the shift register ( 3 ) and the signal output with the Input of a second comparator ( 8 ) provided with the setpoint generator ( 7 ) and the output of the comparator ( 8 ) is connected to the static memory ( 11 ). 4. Circuit arrangement for performing the method according to claim 2, characterized in that the output of the comparator ( 8 ) is connected to a clock counter ( 21 ), the output of which is coupled to the control input of the first switch ( 11 ) and the input of the second switch ( 12 ) with the signal output ( 5 ) of the shift register ( 3 ) and the outputs of the switches ( 11, 12 ) with the input of the static memory ( 11 ). 5. Circuit arrangement according to claim 3 or 4, characterized in that the static memory is connected to a screen device ( 20 ).