DE4311318A1 - Flat panel display unit having pixel activation by low voltage signals - generated for row and columns using pairs of FET devices assigned for each pixel location. - Google Patents

Abstract

A Flat panel display using field emission devices has single pixels that can be individually addressed. The base electrode (23) is separated from the grating (21) and in order that a field emission can be induced the base electrode is coupled to ground by a pair of series coupled FET devices (Qs, Qr). One of the transistors (Qc) receives a signal for the columna and the other a row signal. Each pixel is formed by the emitter coupling (22A-22C). During the activation period the storage difference between the grating (21) and the emitter (22A-22C) is set at a specific level. USE/ADVANTAGE - Provides means of operating with normal integrated circuit technology.

Description

The invention relates to flat panel displays, in particular a matrix addressable flat panel display, in the high pixel activation chip must be switched. The invention enables series and column signal voltages with conventional CMOS, NMOS or other common integrated circuits in terms of logi levels are compatible, with much higher pixel stocks crossing voltages can be reached.

For over half a century, the cathode ray tube (CRT) the display device for the visualization of information par excellence. Whether cathode ray tubes already in this period with regard to their special len properties have been significantly improved, especially with regard to Color, brightness, contrast and resolution, these devices remained as before, voluminous and power-consuming to a large extent. With the need for portable computers grew accordingly nis, to have display means available that are not only through low weight and compact design, but can also be operated with low power. Although Liquid crystal displays are currently practically everywhere in laptop computers directions are used, however, they suffer from a minor Contrast, compared to cathode ray tubes, a limited one Viewing angle range, with significant power consumption specifically added to the color versions of these displays, so that its use for battery operation is hardly recommended. Compared to Cathode ray tubes of the same screen size are the liquid crystal Color display devices are much more expensive.  

Concentrate due to the disadvantages of liquid crystal display devices developments in industry are very much focused on the thin layer field emission display devices. Flat panel displays that are in this technology have a matrix addressable Field of tapered thin film cold field emission cathodes in Combination with a fluorescent screen. The phenomenon of the field emission was discovered in the 1950s, and significant for created by numerous people, for example Charles A. Spindt from SRI International, have improved the technology so that the Prospects, cheap, low-power, high-quality solution and high contrast, flat full color display to be able to produce directions are promising. However, remains Lots of work to do to get the technology to the commercial goal to promote len evaluability.

There are a number of problems associated with the currently available matrix addressable field emission display devices. Heretofore, such displays have been constructed so that a column signal activates a single conductive beam from within the grid, while a series signal activates a conductive strip within the emitter base electrode. At the intersection of an activated column with an activated row, there is then a grid-emitter voltage difference which is sufficient to induce field emission, with the result that the associated phosphor lights up in the phosphorescent screen. In Fig. 1, which is a representative representation of the current structure of the device, three grid strips (grid) 11 A, 11 B and 11 C intersect with a trio of emitter base electrode (row) strips 12 A, 12 B and 12 C. In this illustration, each row-column interface (the equivalent of a single pixel or picture element within the display device) contains sixteen field emission cathodes (hereinafter "emitter") 13 . In practice, the number of emitter tips per pixel can fluctuate greatly. The tip of each emitter tip is surrounded by a grating strip opening 14 . For field emission to occur, the voltage difference between a row conductor and a column conductor must be at least as large as a voltage that corresponds to acceptable field emission levels. The intensity of the field emission depends very much on various factors, the most important of which is the sharpness of the cathode emitter tip and the strength of the electric field at the tip. Although a level of field emission suitable for the operation of flat panel display devices has been reached with emitter-lattice voltages of only 80 volts (this number is expected to decrease in the coming years as the emitter structure and manufacturing technology improve) , the emission voltages will still be significantly greater than 5 volts in the future, which corresponds to the standard level "1" in CMOS, NMOS and TTL technology. So if the field emission threshold voltage is 80 volts, the row and column lines must be designed so that they can switch between 0 and either +40 or -40 volts to come to an interface voltage difference of 80 volts. Consequently, it is necessary to cause high-voltage switching in these row and column lines. Consequently, there is not only the problem of developing suitable drivers for switching such high voltages, but also the problem of excessive power consumption due to the capacitive coupling of row and column conductors. That is: the higher the voltage on the lines, the greater the power that is required to drive the display device.

Suffer in addition to the problem of switching high voltages Aperture display devices due to the possibility of emitter Lattice shorts at a low manufacturing yield and less Reliability. Such short-circuit phenomena influence the Voltage difference between the emitters and the grating within the entire field and can very well become completely useless field, either because of so much power is consumed that the power supply is not sufficiently high Can provide voltage to induce field emission, or because actually so much heat is generated that part of the field melts.

What is needed is a new type of field emission display -  Architecture that overcomes the problems of switching high voltages det and significantly alleviates the problem of emitter lattice short circuits and furthermore the power consumption of the display device puts.

The present invention provides a method for switching one high pixel activation voltage with low signal voltages that are compatible with the conventional levels of CMOS, NMOS and other integrated circuit technologies. Although that Method was developed to get the high lattice emitter span needed control difference required to induce field emissions the method presented here can also be used with everyone other matrix addressable display device (e.g. Vacuum fluorescence display, electroluminescence display or plas display), in which high pixel activation voltages are switched Need to become. Here, however, the invention is intended in connection with a field emission display are explained due to the potential Advantages of this type of display device over other displays devices.

Instead of connecting the columns and rows directly to the cathode field, they are used to open-control at least one pair of field effect transistors (FETs) connected in series, each pair coupling the base electrode of a single emitter node to a potential in the conductive state, which is sufficiently low with respect to a constant potential applied to the grid to induce field emission. Each row / column interface (ie, each pixel) within the display device can include multiple emitter nodes to improve manufacturing yield and product reliability. In a preferred embodiment, the grid of the field is kept at a constant potential (V _FE ), which is consistent with reliable field emission when the emitters are at ground potential. Individual base electrodes can be grounded through a pair of field effect transistors connected in series by applying a signal voltage to both the row and column lines associated with that emitter node. One of the FETs connected in series is open-controlled by a signal on the row line, the other FET is open-controlled by a signal on the column line. For clarification, it should be said that in a preferred embodiment of the invention, each picture element contains several emitter nodes and each emitter node has several cathode emitters. Each row / column interface thus controls several pairs of FETs connected in series and each pair controls a single emitter node that contains several emitters.

In one embodiment, the grating is isolated from each emitter base. A pixel is turned off (ie brought into a non-emissive state) by turning off one or both or both of the FETs connected in series. From the moment at least one of the FETs becomes non-conductive (ie, the gate voltage V _GS drops below the device threshold voltage V _T ), electrons are derived or discharged from the emitter tips corresponding to that pixel until the voltage difference between the bases and the grid is just below the emission threshold voltage.

In another embodiment of the invention, each emitter base node is coupled to the grid via a current-limiting field-effect transistor, the transistor representing a continuous low current path and having a threshold voltage of V _T. While the base is normally at a potential of V _GERID - V _T , the voltage difference between the grid and each emitter (generally below one volt) is _insufficient to cause field emission. Field emission also occurs when the emitter base is grounded through a ground path that is controlled by the two FETs connected in series at a row and column interface. In order for the ground path to become active, both row and column FETs must be turned on at the same time (ie the gate voltage on each field effect transistor must be greater than the device threshold voltage). The use of current limiting transistors to couple each emitter base node to the grid provides more precise switching time control when needed.

According to a further embodiment of the invention, a Stromre gulation resistance in series with each pair of series connected Low-voltage switching MOSFETs laid. As stated above, cop Each MOSFET pair has one or more field emitter tips having emitter nodes on ground. The resistance is right on the Ground rail and connected to the source of the MOSFET that of is the farthest away from the emitter node. Because the current regulation resistor is placed directly on the ground rail, you can reach stable current values regardless of the cathode voltage within a wide range of cathode voltages.

In yet another embodiment of the invention, the Current path, which leads over the two FETs connected in series, at Each emitter base node has a fuse that is used in the test can be melted if a base-emitter short circuit exists within the emitter node in order to shorten the to separate the closed knot from the rest of the field and thereby the Increase production yield and power consumption of the field to minimize. Other functional nodes work within the pixel but still further. It can also be used to control brightness achieve the gate voltages of each FET in the ground path varies, which in turn adjusts the emission current.

In all embodiments of the invention, the current for each pixel across the series connected FETs in at least one Regulated emitter electrode ground path. This feature improved in the degree of uniformity of brightness over the entire range display area away. The brightness level is controlled in a times by varying the gate voltage of each FET. In addition, low-voltage switching at the pixel level improves the Working speed of the display devices. If you use the Architecture in which a display line management is activated and all Columns are activated at the same time, so there is a gray gradation by achieving the duty cycle in each column signal varies during the period of activation of the row line.

In the following, exemplary embodiments of the invention are described with reference to the Drawing explained in more detail. Show it:

Fig. 1 is a simplified perspective view of the structure of the grid and emitter base electrodes in a conventional flat panel field emission display device;

Fig. 2 is a schematic representation of a first embodiment of a single emitter node within the new flat panel field emission display structure, with the emitter base electrode separated from the grid;

Figure 3 is a schematic sketch of a second embodiment of a single emitter node within the new flat panel field emission display structure, with a current limiting transistor connecting the emitter base electrode to the grid.

Fig. 4 is a schematic representation of a first embodiment of a single emitter node within the low voltage switching field emission display structure in which a current regulating resistor is installed;

5 is a plan view of a possible layout for new flat panel display architecture, wherein seen from the illustration, as a plurality of emitter node in a single row-column interface (ie, a single pixel) are mountable Fig. and

Fig. 6 is a plan view of a possible layout for the low voltage switching field emission display device with current regulation resistor.

FIG. 2 is a single emitter node of the first exporting approximate shape of a new field emission display structure characterized by a (also known as a first pixel element hereinafter) conductive grid 21, which extends continuously over the entire field and held at a constant potential V _GRID . Each pixel element within the field is illuminated by an emitter group. To improve product reliability and manufacturing yield, each emitter group consists of several emitter nodes, each node in turn containing several field emission cathodes (also referred to as "Feldemit ter" or just "emitter"). Although having individual emitter node of FIG. 1, only three emitter (22 A, 22 B, 22 C), in practice the number may be much higher. Each of the emitters 22 is connected to a base electrode 23 which is common to only the emit ter of a single emitter node. The combination of emitter and base electrode is also referred to here as a second pixel element.

In the embodiment shown in FIG. 2, the base electrode 23 is separated from the grid 21 . To induce field emission, base electrode 23 is grounded through a pair of field effect transistors Q _C and Q _R connected in series. Transistor Q _C is open controlled by a column line signal S _C , while transistor Q _R is open controlled by a row line signal S _R. The usual logic signal voltages for the CMOS, NMOS, TTL and other technologies of integrated circuits are consistently 5 volts or less and can be used here for both the column and the row line signal. It has been noted that transistor Q _C can be replaced by two or more FETs connected in series, all of which are open controlled by the same column line. Similarly, transistor Q _{R can be} replaced by two or more FETs connected in series, all of which are open controlled by the same series line. Similarly, other FETs open controlled by control logic can be arranged in series within the ground path. A pixel (picture element) is switched off (ie brought into the non-emitting state) by switching off either one or both of the FETs (Q _C and Q _R ) connected in series. From the moment at least one of the FETs becomes non-conductive (ie, the gate voltage V _GS drops below the device threshold voltage value V _T ), electrons from the emitter tips corresponding to that pixel are discharged until the Voltage difference between the base and the grid is just below the emission threshold voltage value.

Fig. 3 shows a second embodiment of an emitter node, the emitter node is functionally and structurally similar to the first embodiment of the emitter node of FIG. 2. The main difference is that the base electrode 23 is coupled to the grid 21 via a current-limiting N-channel field effect transistor Q _L , which has a threshold voltage V _T. Both the drain and the gate of the transistor Q _L are directly coupled to the grid 21 . The channel of the transistor Q _L is dimensioned such that the current is only limited to such a value that is required to reset the base electrode 23 and the associated emitters 22 A, 22 B and 22 C to a potential which is essentially equal the value V _GRID - V _T at a speed sufficient to ensure an adequate gray scale resolution.

Fig. 4 shows a single emitter node similar to the first embodiment according to FIG. 2, but here the emitter node is connected to ground via a pair of field effect transistors Q _C and Q _R connected in series and also via a current regulating resistor R. Resistor R is between the source of transistor Q _R and ground. In the likely case that the grid voltage is greater than 20 volts, the closest MOSFET device (in this case, the MOSFET Q _C ) to the grid 21 must be a high voltage device to prevent cathode substrate breakdown . The breakdown security of such a high-voltage transistor depends on the transient voltage of the emitter node.

As shown in FIGS. 2, 3 and 4, there is a fusible connection in series with the lowering current path, which leads from the base electrode 23 via the transistors Q _C and Q _R to ground. The fusible link FL can be burned through during the test of the component if there is a base-emitter short circuit within this emitter group, so as to separate the short-circuited group from the rest of the field and thus increase the component yield and reduce the power consumption of the display panel. It should be noted that the position of the fuse FL within the current path has no effect as far as the circuit technology is concerned. That is, the purpose of disconnecting a shorted node is accomplished regardless of whether the fuse between transistors Q _C and Q _{R is} between base electrode 23 and the pair of transistors grounded, as shown in Figure 2, or between ground and the pair of transistors connected to ground.

Referring again to Figs. 2, 3, and 4, it should be noted that the gradation of gray (i.e., varying the pixel lighting) in a working display device can be accomplished by considering the duty cycle or duty cycle (the time period in which the emitters within a Pixels actually emit, expressed as a percentage of full screen time) varies. The brightness control can be carried out by varying the emitter current, for example by changing the gate voltages of either the transistor Q _C or the transistor Q _R or both transistors.

Fig. 5 shows a simplified layout for multiple emitter nodes for each row-column interface of the display field. A pair of polysilicon row lines R ₀ and R ₁ intersect perpendicularly with metal column lines C ₀ and C ₁ and with a pair of metal ground lines GND ₀ and GND ₁ . The ground line GND ₀ belongs to a column line C ₀ , while the ground line GND ₁ belongs to the column line C ₁ . Each row and column interface (ie, for each individually addressable pixel within the display device) there is at least one row line extension which forms the gates and the gate junctions for multiple emitter nodes within that pixel. For example, the extension E ₀₀ belongs to the interface of the row R ₀ with the column C ₀ , the extension E ₀₁ belongs to the interface of the row R ₀ with the column C ₁ ; the extension E ₁₀ belongs to the interface of the row R ₁ with the column C ₀ ; and the extension E ₁₁ belongs to the interface of the row R ₁ with the column C ₁ . All of these interfaces function in an identical manner, so that only the components in the interface zone R ₀ - C ₀ are explained in detail here.

According to FIG. 5, the cutting zone R ₀ carries - C ₀ three emitter node EN _1, EN ₂ and _EN3. Each emitter node contains a first active area AA ₁ and a second active area AA ₂ . A metal ground line GND makes contact with one end of a first active region AA ₁ at a first contact CT ₁ . In combination with the first active region AA ₁ , a first L-shaped polysilicon strip S _{1 forms} the gate of the field effect transistor Q _C (cf. FIG. 2). The metal column line C ₀ makes contact with the polysilicon strip G ₁ at a second contact point CT ₂ . The polysilicon extension E ₀₀ forms the gate of the field effect transistor Q _R (see again FIGS. 2 and 3). A first metal strip MS ₁ connects the first active area AA ₁ to the second active area AA ₂ by contacting via a third contact CT ₃ or a fourth contact CT ₄ .

The section of the metal strip MS ₁ , which lies between the third contact CT ₃ and the fourth contact CT ₄ , forms the fusible link FL. The emitter base electrode (see position 23 in FIGS . 2 and 3, since the emitter base electrode is not shown in this layout) is coupled to the metal strip MS ₁ . A second L-shaped polysilicon strip S ₂ forms the gate of the current limiting transistor Q _CL , and a second metal strip MS ₂ is connected at a fifth contact CT ₅ to the second polysilicon strip S ₂ , and via a third contact CT ₆ with connected to the second active area AA ₂ . The grid plate (see position 21 in Fig. 2 and 3, since the grid plate is not shown in this layout) is connected to the second metal strip MS ₃ . It must be emphasized that the layout according to FIG. 5 is only exemplary.

Referring now to Fig. 6, a possible layout for the first embodiment of the emitter node in combination with a current regulating transistor of the ground path is shown. Although the layout of Fig. 5 very similar, there is a difference in that is formed as no current limiting transistor Q _L through an active region AA ₂ and the strip S _2, which acts as the gate of the Strombegrenzungstransi stors Q _L. In this layout, the emitter tips E ₁ and E _{2 are formed} directly on the active area AA ₂ . Another difference is the presence of the current regulating resistor R, which is here in the form of a C-shaped polysilicon strip S _R. One end of the C-shaped polysilicon strip S _R is in direct contact with the first active area AA ₁ , while the other is in contact with a metallic ground line or rail GND at a first contact point CT ₁ . Although most of the C-shaped polysilicon strip is lightly doped with a level that suitably sets the resistance value for the resistor R, its ends are heavily doped so that there is an effective ohmic contact.

Equivalent layouts are possible, and other resistor and conductor materials are possible instead of the polysilicon and metal structures in FIGS. 5 and 6.

Claims (22)

1. A method of operating a field emission display device with which individual pixels (picture elements) of the display are individually addressed, the field emission display device comprising: a plurality of row address conductors (R ₀ , R ₁ ) which intersect a plurality of column address conductors (C ₀ , C ₁ ), the interfaces of a single row address conductor with a single column address conductor corresponding to a single pixel of the display, and groups of field emission cathodes, each group corresponding to a specific pixel, characterized by the following steps:

• - in periods of time in which a particular pixel is inactive, a first voltage difference is maintained between the grid ( 21 ) and the cathode group ( 22 A- 22 C) belonging to this pixel, the first voltage difference being insufficient for field emission;
• - During such periods in which the pixel is active, the voltage difference between the grid ( 21 ) and the cathode group belonging to this pixel ( 22 A- 22 C) is raised to a second voltage difference, which is sufficient for a field emission, for which the The voltage difference is increased by pulling down the potential at the cathode group belonging to the pixel via at least one lowering current path, which is openly controlled by a row signal (S _R ) and column signal (S _C ) belonging to the pixel.

2. The method according to claim 1, wherein the potential to act fourth pixel belonging cathode group to ground potential is pulled down.   3. The method according to claim 1, wherein each lowering current path comprises: a plurality of field-effect transistors (Q _C , Q _R ) connected in series, at least one of which is a row signal (S _R ) and the rest of a column signal (S _C ) is controlled open. 4. The method of claim 3, wherein the for the series signal and the column signal used voltage level compatible with übli Chen are logical signal voltages. 5. The method according to any one of claims 1 to 4, characterized in that each cathode group is charged via at least one current-limiting conductive path from the grid ( 21 ) to each cathode group during inactive phases of the pixel to a voltage value in the vicinity of the grid voltage. 6. The method of claim 5, wherein each current limiting path comprises: an N-channel field effect transistor (Q ₁ ) whose drain and gate are coupled to the display grid ( 21 ) and whose source is coupled to an emitter base electrode ( 23 ) . 7. The method of claim 1, wherein each cathode group belonging to a single pixel has a plurality of emitter nodes (EN ₁ -EN ₃ ), each node having its own emitter base electrode ( 23 ) on which a plurality of field emission cathodes ( 22 A- 22 C) are located. 8. The method of claim 7, wherein each emitter base electrode ( 23 ) has a lowering current path and each lowering current path contains a fusible link (FL) which is burnable during the testing of the component, so that the emitter nodes, the one or more emitters Grid shorts, can be functionally separated from the display device. 9. The method of claim 8, wherein each pixel is plural has emitter groups that can be separated by melting.   10. The method according to claim 3, in which changes in the pixel Hel brightness occur in that the gate voltages in at least one of the field effect transistors (S _C , S _R ), which contain the sink current paths of the pixel in question, are varied so that the emission current for the emitters belonging to this pixel is varied. 11. A field emission display device comprising:
several row address conductors (R ₀ , R ₁ );
several column address conductors (C ₀ , C ₁ );
wherein the row address conductors intersect the column address conductors, and the interface of a single row address conductor with a single column address conductor within the display device belongs to a single pixel (picture element);
a grid ( 21 ) which is common to the entire display device and which is continuously kept at a first potential;
Groups of field emission cathodes ( 22 A- 22 C), each group belonging to a particular pixel and each group being kept at a second potential close to the first potential during inactive phases of the pixel to suppress field emission, and each group is maintained at a third potential during active phases of the pixel, which is sufficiently low with respect to the first potential to induce field emission; and
wherein at least one sinking current path is provided between the cathode group of each pixel and a node held at a fourth potential which is less than or equal to the third potential, the path in response to signals on a row address conductor and column address conductor (S _R or S _C ) can be activated in order to enable switching of the potential applied to the cathode group belonging to this pixel between the second potential and the third potential. 12. The apparatus of claim 11, wherein the fourth potential lies between ground potential and the second potential. 13. The method of claim 11, wherein each cathode group belonging to a single pixel contains a plurality of emitter nodes (EN ₁ - EN ₃ ), each node having its own emitter base electrode ( 23 ) on which a plurality of field emission cathodes ( 22 A- 22 C) lie. 14. The apparatus of claim 13, wherein each emitter base electrode ( 23 ) has its own lowering current path, and each lowering current path has a fusible link (FL) that is burnable during device testing so that those emitter nodes that are one or have multiple emitter lattice short circuits that are functionally separable from the display device. 15. The apparatus of claim 11, wherein the lowering current path comprises: a plurality of series-connected field effect transistors (Q _C , Q _R ) of which at least one of a signal on the associated row address conductor (S _R ) is open-controlled, while at least one the rest is open-controlled by a signal on the associated column address address (S _C ). 16. The apparatus of claim 11, wherein each sinking current path comprises: a current regulating resistor (R) and at least two field effect transistors (Q _C , Q _R ), the resistor and the transistors being connected in series and the resistor directly coupled to the node is while at least one of the transistors is open-controlled by a signal (S _R ) on the associated row address conductor, and at least one further transistor can be activated in response to a signal (S _C ) on the associated column address conductor. 17. The apparatus of claim 15 or 16, in the changes of Pixel brightness can be achieved by moving the gate voltages on at least one of the field effect transistors varies, that each of the sinking current paths of a particular pixel contains, so that the emission current varies within the emitters of that pixel becomes. 18. The device according to one of claims 11 to 17, in which the group of field emission cathodes ( 22 A- 22 C) is charged to the second potential via at least one current-limiting, conductive path between the grid and the emitter when the associated pixel is deactivated, the conductive path also serves to minimize the current flowing between the grid and emitter during the activation phases of the pixel. 19. The apparatus of claim 18, wherein the current limiting conductive path comprises an N-channel field effect transistor (Q ₁ ), the drain and gate of which are coupled to the display grid ( 21 ) and the source of which is coupled to a single emitter base electrode ( 23 ) . 20. Flat panel display comprising:
several row address conductors (R ₀ , R ₁ );
several column address conductors (C ₀ , C ₁ );
the row address conductors intersect the column address conductors and the interface of a single row address conductor with a single column address conductor belongs to a single pixel (picture element) within the display;
first and second elements provided for each pixel, the pixel generating light emitted when a voltage difference between the two elements (hereinafter the intermediate element voltage difference) is applied which exceeds a pixel activation threshold;
a sink node held at a constant potential;
wherein at least one selectively activatable lowering current path lies between the second pixel element and the lowering node and the path coupling the node to the second pixel element forms, when activated, an intermediate element voltage difference which exceeds the pixel activation threshold value, and the path the node from that decouples the second pixel element when the path is deactivated, thereby creating an inter-element voltage difference that does not exceed the pixel activation threshold. 21. The display of claim 20, wherein the lowering current path comprises:
a plurality of series-connected field effect transistors (Q _C , Q _R ), of which at least one is open-controlled by a signal on the associated row address conductor (S _R ), while at least one of the others is open-controlled by a signal on the associated column address conductor (S _C ) becomes. 22. A method of controlling the pixel activation voltage in a row and column addressable flat panel display device having a plurality of row address conductors (R ₀ , R ₁ ) intersecting a plurality of column address conductors (C ₀ , C ₂ ) so that the interface of a single row address conductor with a single one Column address conductor belongs to a single pixel (picture element) in the display and each pixel has a pixel activation voltage,
characterized,
that a first signal voltage (S _R ) is selectively applied to individual row address conductors and a second signal voltage (S _C ) is applied to individual column address conductors, the first and second signal voltages being less than half of the pixel activation voltage.