DE4202016C1 - Channel clock generation for data transmission - setting data w.r.t. rising edge, and using pulse from counter to generate channel clock in second counter under control of evaluation unit - Google Patents

Abstract

The channel clock generation method involves feeding a preceding clock, which is a multiple of the channel clock, to two counters (2A,2B). The first counter is set by each leading edge of the channel data and is coupled to an evaluation device (6) controlling the second counter (2B) at its output. The evaluation device (L) receives a pulse from the first counter (2A) at data centre, the channel clock (SUBC) being provided by the second counter (2B). The latter is initially set by the leading data edge of the channel data (SUBD). The evaluation device (L) verifies that the clock edge of the channel clock (SUBC) lies within a given range. The second counter (2B) is set by a pulse from the first counter (2A) when no clock edge is present is this range. ADVANTAGE - Provides synchronous fitter-free channel clock.

Description

The invention relates to a method for generating a Channel clock from an existing clock according to the generic term of claim 1 and an arrangement for generating a Channel clock from an existing clock according to the generic term of claim 2.

EP 02 61 428 A2 describes an arrangement for Clock recovery known. This arrangement has one Edge detector that generates a pulse when the received data change from "0" to "1" or vice versa. A first counter is provided, which counts with one cycle, which is an integer multiple of the transfer rate of the received data and from each pulse of the edge detector is set. An evaluation unit for processing the output the first counter is provided. There is also a second one Counter provided the output of the evaluation unit receives and counts with the clock of the first counter. A Phase comparator is provided, which decides how the recovered clock to a pulse from the second counter is output, lies and is a variable frequency divider provided, which is controlled by the phase comparator and off the clock with which the first counter counts, the recovered Clock generated.

A disadvantage of the arrangement known from EP 2 61 428 A2 is that the recovered clock is only generated from data center data can be varied with the duty ratio of the data.  

In addition, the data jitter on the recovered clock transfer.

It is an object of the invention, a method and an arrangement to generate a channel clock from an existing clock to indicate with the one as synchronous as possible and jitter-free channel clock can be generated.

The task is carried out with regard to the procedure by a procedure with the features of claim 1 and with respect to the arrangement an arrangement with the features of claim 2 solved. Advantageous further developments of the arrangement are See subclaims.

It is assumed that there is a clock, the one n-number multiple of the channel clock. The channel clock can thus generated by clock division.

With an unset counter or divider, the location of the Clock edge of the channel clock for the data is not predetermined will.

However, if you trigger the divider on the data edges, then the jitter of the data is fully transferred to the clock because with each data edge of the divider is retriggered. A single triggering of the divider and subsequent "free run" is also not possible for reasons of interference immunity. Around To achieve a necessary jitter reduction would have to first case, the clock generated by the divider, by a additional PLL can be smoothed.

Preferably the counter or divider is the channel clock generated, triggered by the first incoming data edge, that the rising clock edge of the channel clock exactly in the Data center comes to rest. Then the counter is or  Divider in "free run" mode. If a new data edge arrives, it is checked whether within a predefined Monitoring area a clock edge occurs. If there is one The clock edge continues to run in the "free run". He follows no clock edge, the counter becomes new in the middle of the data triggered. This solution allows the data to be stored in one jitter certain area without affecting the Channel clock takes.

The invention assumes that an existing clock is present, the existing clock being an n-number multiple of the channel clock to be generated; n is an even natural number. There are two counters that count modulo n with the existing clock. The first counter measures the middle of the data; for this purpose it is set by each rising data edge of the channel data and emits a pulse at the counter reading n / 2 . The second counter runs freely and changes its initial state at the counter readings n / 2 and n. When it is switched on, it is set once with the rising edge of the channel data. Its initial state corresponds to the channel clock to be generated. An evaluation unit, to which the pulse of the first counter is fed, is provided. This evaluation unit checks whether the clock edge, which corresponds to the counter reading n / 2 of the channel clock, is in a monitoring area, that is, whether the ascending or the falling clock area is in the area. The monitoring area is determined as a function of the rising edge of the channel data and specifies how much the temporal position of channel data and channel clock can differ.

If the check shows that there is a clock edge in the monitoring area, the second counter continues to run unaffected. However, if there is no clock edge in the monitoring area, the second counter is reset by means of the n / 2 pulse of the first counter, specifically to the counter reading n / 2 . The check can be carried out immediately after receipt of a data edge. This is done by comparing the counter reading of the second counter with the possible counter readings at which a clock edge is a monitoring area. This means that a decision can be made before the middle of the data. The second counter can be set with the first pulse of the first counter after the corresponding data edge, that is, for example, still within the monitoring range. The channel clock therefore responds very quickly. The channel data are sampled again with the channel clock and the synchronized data are output at an output.

A particularly important application for the invention lies ahead for messaging systems with subchannels without their own Clock recovery for the subchannel.

For example, in a 34 Mbit CMI data stream Code rule violation in a 256 kbit subchannel. The clock for the subchannel can be divided by the 34 MHz System clock (34 MHz / 134) are generated. For the subchannel should therefore come from the main channel clock or system clock synchronous jitter-free subchannel clock can be generated. The System clock for the main channel is done in a conventional manner generated.

A clock for the sub-channel is created by dividing the system clock generated. The clock edge of the sub-channel clock is thereby for example in the middle of the data. The generated sub-channel clock is fixed to the higher-frequency system clock bound. If the sub-channel data is then above the sub-channel clock jitter, this is for a range from 0 to  (n-2) / n UI permissible (n = divider factor of the clock divider) without the data jitter is transferred to the clock. Is the Data jitter larger than the permissible range (e.g. due to Incorrect synchronization), the sub-channel clock divider becomes new triggered (edge in the middle of the data).

Since the circuit allows a predefined range in which the sub-channel clock edge may vary, this means at rigid sub-channel clock that the data edges in this area may vary (jitter). So the sub-channel clock remains rigid (jitter-free) if the data jitter matches the permitted Area, the surveillance area. This The range is (n-2) / n UI.

An embodiment of the invention is based on the Drawings explained. Show it:

Fig. 1 is a block diagram of an arrangement according to the invention and

Fig. 2 shows the various clocks and signals.

The circuit consists of two counters ZA, ZB and one Evaluation unit L. The entire circuit concept is fully synchronized to a higher-frequency system clock SYSC bound. The counter ZA is increased by the Data edge of the sub-channel data SUBD triggered and measures the Middle of data. If the sub-channel data SUBD n system clock cycles are wide, the counter ZA gives one Counter reading of n / 2 a pulse to the evaluation unit, n / 2 is thus coded out from the Q outputs of the counter ZA. The counter ZB generates the sub-channel clock SUBC. The The initial state of the counter ZB changes when the counter reading from n / 2 from "low" to "high" and at count n from "high" to "low". The counter ZB counts up to n (n = divisor factor  of the sub-channel clock) and is evaluated by the evaluation unit L triggered.

The evaluation unit L monitors whether in a predefined Monitoring area (measured from the rising data edge) one rising clock edge of the sub-channel clock SUBC takes place. Becomes no clock edge expected in the monitoring area, triggers the evaluation unit the counter ZB in such a way that the Clock edge is placed back in the middle of the data. That means however, the position from clock to data edge can be in the whole Monitoring area ÜB vary without new counter ZB is triggered. The surveillance area thus defines the allowable data jitter.

The system synchronizes in the following way: The first sub-channel data edge triggers counter ZA and over the Evaluation unit L also counter ZB. The edge of the sub-channel Taktes is now in the middle of the data. With the next one Data edge, the data center is determined by counter ZA and this information is transmitted to the evaluation unit L. As a result, the evaluation unit L initiates a query of the Counter status counter ZB and determines whether in Monitoring area ÜB a clock edge occurs. Is a Clock edge within the monitoring area ÜB, running Counter eg in "free run" mode.

When the counter example that is, until n is one, and the clock edge of the sub-channel clock SUBC is produced at n / 2, so (query of counter B at time n / 2 from data edge) can be prepared by the interrogation of the meter reading, the exact position of the sub- Channel clock edge can be determined. The system therefore does not have to occur until the end of the monitoring area ÜB for the event "clock edge" until the end of the monitoring area ÜB. This predetermination of a future event enables the system to react at a point in time at which the data can still be clocked safely (data center).

So the expected clock edge is outside of the overshoot area, the counter ZB becomes new in the middle of the data triggered. This also results in a data jitter that is larger than the permissible range, no data loss. However, this error case creates a phase jump in the Sub-channel clock SUBC.

The present circuit clocks the sub-channel data SUBD again with the sub-channel clock SUBC, so that the data SUBD _S synchronized to the jitter-free sub-channel clock are output.

Claims (5)

1. A method for generating a channel clock from an existing clock, the existing clock being n times the channel clock, n even natural number, with two counters that count modulo n with the existing clock, the first counter of each rising data edge the channel data is set, the outputs of the first counter are fed to an evaluation unit and the second counter is controlled by the evaluation unit, characterized in that a pulse is emitted from the first counter (ZA) to the evaluation unit (L) in the middle of the data that the channel clock (SUBC) is generated by the second counter (ZB) by the counter (ZB) changing its initial state at counter reading n / 2 and counter reading n that the second counter (ZB) once, when switched on, with the rising data edge of the channel data ( SUBD) is set and then runs freely that the evaluation unit (L) checks whether a clock edge of the channel clock (SUBC) is in a monitor ngs range (ÜB) occurs and that the second counter (ZB) is reset by means of the pulse from the first counter (ZA) if no clock edge occurs in the monitoring area (ÜB). 2. Arrangement for generating a channel clock from an existing clock with the following features:

• a) the existing clock (SYSC) is an n-numbered multiple of the channel clock (SUBc) (n = 2 · m, mε N);
• b) two counters (ZA, ZB) are provided, which count modulo n with the existing clock;
• c) an edge detector is provided which emits a pulse with each rising data edge of the channel data (SUBD) with which the first counter (ZA) is set;
• d) there is an evaluation unit (L) which receives the outputs of the first counter (ZA) and controls the second counter (ZB); characterized by the following features:
• e) the first counter (ZA) emits a pulse to the evaluation unit (L) at the middle of the data, corresponding to the counter reading n / 2 ;
• f) the edge detector sets the second counter (ZB) once, when switching on;
• g) the second counter (ZB) runs after setting the counter (ZB) until it is set again;
• h) the second counter (ZB) generates the channel clock (SUBC) by changing its initial state at counter reading n / 2 and at counter reading n;
• i) the evaluation unit (L) checks whether the clock edge of the channel clock (SUBC), which corresponds to the counter reading n / 2 of the second counter (ZB), occurs in a monitoring area (ÜB) and sets the second counter (ZB) by means of the pulse from the first counter (ZA) if no clock edge occurs.

3. Arrangement according to claim 2, characterized in that the Evaluation unit at the beginning of the monitoring area (ÜB) or immediately after the data edge due to the counter reading of the second counter (ZB) checks whether within the Monitoring area (ÜB) another clock edge of the  Channel clock (SUBC) occurs and that the second counter (ZB) possibly by means of the pulse of the first counter (ZA), which is in the same monitoring area (ÜB) is set. 4. Arrangement according to one of claims 2 or 3, characterized characterized in that the surveillance area (ÜB) is symmetrical to the pulse from the first counter (ZA) is arranged. 5. Arrangement according to one of claims 2 to 4, characterized in that it is provided to scan the channel data (SUBD) again with the channel clock (SUBC) and that the synchronized data (SUBD _S ) are output at an output.