DE4131061C1 - Switching procedure for external reference pulse signal in telephone exchange - conducting external reference signals to module delivering reference pulse series for synchronising central pulse generator or clock - Google Patents

Abstract

The method enables one of a number of external reference time signals in an exchange system. At least two external reference time signals from external reference sources are passed to the exchange system at at least one reference time supply circuit (LTU4,TMD41) to synchronise central timer (CCG). One external reference signal is selected and switched into the central timer (CCG). A controller (CCGC) allocated to the central timer (CCG) connects a connector lead (LTU4-CCG) between the timer (CCG) and an open switch (S) in the supply circuit (LTU4,TMD41). The central timer (CCG) checks the connected lead (LTU4-CCG) for interference. In the absence of interference the controller (CCGC) closes the switch (S) and thus switches the selected external reference signal to the central timer (CCG). ADVANTAGE - Eliminates interference in synchronising central timer of exchange system.

Description

The invention relates to a method according to the preamble of Claim 1.

In synchronous digital telecommunications networks are central clock facilities of the individual digital switching systems here archived synchronized according to the master / slave principle. Here is a single frequency determining for the entire network Clock generator (master clock) provided. On its clock frequency become the central clock devices of the networked operator systems synchronized. A switching system can ne plurality of external reference clock signals are supplied where in the switching system exactly one external reference clock i gnal to synchronize its central clock device chooses. Such a switching system is in a special way "telcom report" and Siemens magazine COM, 1985, pages 58 to 66, ISBN 3-8009-3846-4.

After selecting exactly one external reference clock signal this to the central clock facility of the respective operator switch system. On the connecting line between the input module of the switching system, which the external Reference clock signal is supplied, and the central clock genes However, malfunctions can occur, for example Crosstalk or an unselected reference clock signal, the Z. B. with an incorrectly closed switching device on the module of the switching system that supplies the reference clock is switched through to the central clock generator. A Connection of the selected external reference clock signal via closes such a faulty connecting line the synchronization of the central clock device.  

From the German patent application DE 39 32 700 A1 is already be a procedure for the interconnection test of a switching network knows. In the known method, individual connections Test information fed in at the entrance of the switching network, who know the relevant switching matrix input and time channel drawing sender address and a coupling include field output and time channel designating destination address. The test information is either transmitted before Commissioning of a connection once or during the existing connection at periodic intervals in nor sometimes used for signaling information Time spans.

The invention has for its object a method of the type mentioned at the outset to indicate disruptions in the Synchronization of the central clock facility of an operator system eliminated.

This task is carried out in a method of the type mentioned at the beginning Art solved by the features of claim 1.

It is to be regarded as essential for the invention that the also connecting line referred to as reference clock path between a module supplying the reference clock and the zentra len clock device is checked for malfunctions. Doing so the central clock device as a test or measuring device used.

According to an advantageous embodiment of the invention provided that, provided that the connecting line from each other connectable line sections, the line section based on the clock device in sections in Rich tion of the switching device for the absence of faults be checked. In this way, any malfunctions localize individual line sections and thus fix specifically.  

Further advantageous embodiments of the invention are in the subclaims and are referred to below described by hand of the figures.

It shows

Figure 1 shows a switching system with a central Taktinrich device to which an external reference clock signal is switched on according to the inventive method.

Fig. 2 is selected, directly involved in the conduct of the process of the invention components of the Ver averaging system of Fig. 1; and

Fig. 3 is a block diagram of a central clock device.

The switching system shown in Fig. 1 is only to the extent necessary to understand the invention. It consists of a switching part SWU and an operational technical unit ADS (Administration and Data Server) not involved in the method according to the invention. The switching part SWU consists of several connection groups LTG1. . . LTG8 (Line Trunk Group), a central switching network CSN (Central Switching Network), a control CC (Common Control) and a central clock device CCG (Central Clock Generator).

The LTG1 connection groups. . . LTG8 consist of connection units LTU1. . . LTU4, a group switching network GSN (Group Switching Network), a service unit SU (Service Unit) and a group control GC (Group Control).

The connection units LTU1. . . LTU4 consist of peripheral modules len, the interface adjustments between the mediator system and the digital or analog environment. As subscriber-oriented device connections come for example to use: digital subscriber line modules, that are ISDN basic connections for digital mono- and multifunctional Terminals or 1-channel connection modules for end devices, such as digi tal voice terminals and operator terminals and analog part slave connection modules for analog voice terminals.

The peripheral modules also include line connections modules that connect to public and private networks or special facilities. These include, for example digital wiring harness assemblies, d. H. ISDN basic connections for ISDN public and cross traffic, digital interfaces units, d. H. Multiplex connections (30 channels each 64 kbit / s), analog wiring harness assemblies, d. H. Line connection modules for analog lines and X.21 subscriber or exchange rate construction groups, d. H. Connection modules for digital lines according to the IDN standard X.21.  

External reference clock signals are sent to the switching system the line connection modules supplied, which in the following as re modules supplying the reference clock.

Several peripheral modules become functional and constructive a connection unit LTU summarized.

A service unit SU is a plurality of line units LTU1. . . LTU4 assigned together. The service unit SU consists of a signaling unit, an audio tone generator and gege also a conference facility.

The signaling unit takes over the character supply of the Systems with audible tones, announcements and the reception of DTMF keys Dialing signs and dialing tones. This function comes with a signal processors realized.

Each connection group has a group control GC which sets the coupling stage GSN. A coupling stage GSN ver binds the four connection units LTU1. . . LTU4 and the service unit SU with each other. It is over eight multiplex channels with the coupling stage CSN and via their connections with whose switching stages GSN again with other switching networks stages connected to GSN.

The coupling stage CSN is built up from units with two time stages MTS (Memory Time Switch) 64 . Each time stage MTS 64 connects any of the 64 incoming and outgoing multiplex channels for voice or data, any two of the 64 times were with each other. The coupling stages GSN and CSN are duplicated, as are their associated controls GC and CC. Group controls GC and central controls CC have the same structure. The heart of every controller is a uniform data processor with a standard operating system. The basis for this is the processor family SAB8086 / 80286 from Siemens and a working memory that can be expanded up to 32 Mbytes, for example.

The memory modules contain highly integrated dynamic RAM Devices and error correction circuits. Data processor and Memory modules are made by a standardized multibus connected. The settings are made via these interfaces to the directly assigned switching network.

For handling the HDLC protocol to the connection units LTU and the service unit SU is a processor for Signali upstream control on the multibus. The message out Exchange with the protocol control in this module takes place via a memory area on the multibus, which is both from the data processor software as well as signaling control Software can be controlled.

The switching system can be designed in such a way that the central clock device CCG generates all the necessary system clocks ("CLOCK"). In the switching system shown in FIG. 1, these are supplied to the units IOCG and IOCC, which will be described later, which have their own clock repeater ("clock repeater") devices. These devices forward the "CLOCK" system clock to the switching network stages GSN or CSN.

The dashed line in the block diagram of FIG. 1 represents a reference clock path, that is to say the connecting line from a module LTU4 supplying the reference clock to the central clock device CCG. The reference clock path is divided into a plurality of line sections, a first line section from the central clock device CCG the unit leads IOCC; a second line section leads from this latter device IOCC to the device IOCG and a third line section leads from the device IOCG to the reference clock supplying module LTU4. These components are shown in Fig. 2.

The method according to the invention is now described in more detail with reference to FIG. 2, which shows a block diagram of those modules of the switching system that are directly involved in the method for connecting an external reference clock signal, and the actual reference clock path. These modules are a peripheral module, in the present case a digital trunk set module TMD41 (Trunk Module Digital), which is integrated, for example, in the connection unit LTU4 shown in FIG. 1, a connection unit control LTUC, an input / output control device IOCG (input / output controller) ) of the connection unit LTG1, which is integrated in the group control GC, an input / output control device IOCC, which sets the central switching network CSN triggered by control commands from the central control CC and the central clock device CCG.

In the TMD41 or TMD42 wiring harness assembly there is the already mentioned switching device S integrated by the Control CCGC is controlled.

The connection unit control LTUC also contains a switch Establishment of LTUCS in systems with redundant units always turns on the active unit, in this case IOCG, not IOCG *.

The devices IOCG, IOCG * contain a switch IOCGS, IOCGS *, the interconnection of neighboring lines cuts IOCC - IOCG and IOCG - TMD41 serves.

The IOCC, IOCC * devices contain multiple switches (Mul tiplexer) IOCCS, IOCCS *, which interconnect the Lei CCG - IOCC with one of the line sections IOCC - LTG1. . . IOCC - LTG8 serve. So you choose the lei tion section of that connection group LTG1. . . LTG8 from that contains the module supplying the reference clock. This is here LTG1. The IOCC facility is with the central clock facility CCG connected.  

It is initially assumed that the switching system to synchronize the central clock device CCG from ex external reference clock sources to min at least a module providing the reference clock, for example TMD41 and TMD42 is supplied. In the following is pre given criteria one of possibly added selected reference clock signals. The Ver drive setsi after selecting an external reference clock gnals one. As a result of the clock selection, the address of the associated module providing the reference clock, here for example show TMD41, over which the external reference clock signal be to be pulled. Starting from this address, ei control assigned to the central clock device CCG CCGC the reference clock distance that is between the zentra len clock device CCG and an initially open switch device S in the reference clock supplying module TMD41 located. The central clock facility CCG checks the connected reference clock path CCG - LTU4 for possible faults stanchions. Such disturbances can be caused, for example, by secondary speak or by mistakenly turned on reference clock signal are formed because of the open switching device S not equal to the selected external and still on reference clock signal to be switched.

The central clock device CCG acts as a testing or measuring device, as will be described with reference to FIG. 3.

If the check shows that there are no faults on the connecting line between the central clock device and the reference clock supplying module, the originally opened switching device S in the reference clock supplying module TMD41 is closed and the selected external reference clock signal is thus switched on to the central clock device CCG. In the present case, the connecting line consists of two interconnectable line sections LTU4 - IOCG, IOCG - (IOCC) - CCG. It can be provided that the device IOCC has a corresponding circuit device, so that in this skin the connecting line consists of three interconnectable line sections LTU4-IOCG, IOCG-IOCC and IOCC-CCG. In the structure of the telecommunications switching system shown in FIG. 2, the line section CCG - (IOCC) - IOCG is checked in a first method step and then the line section IOCG - LTU4 is checked for the absence of faults. If, on the other hand, the IOCC device contains - as already mentioned - a corresponding switching device, so that the reference clock path consists of three interconnectable line sections, the first line section CCG - IOCC is used in a first step, the first line section CCG - IOCC in a second step checked for possible faults together with the second line section IOCC-IOCG, which is immediately adjacent to the first line section CCG-IOCC. The IOCGS switch is open until the test is completed and is closed in the absence of faults. In a third method step, the already tested line sections CCG-IOCC-IOCG are checked for possible faults together with the immediately adjacent line section IOCG-TMD41 (LTU4, FIG. 1). The switch ter S is open until the end of the test and is closed with a positive test result.

This section-by-section check of the reference clock results Do not stretch faults, so that is in the reference clock delivering module TMD41 arranged switching device ge closed and thus the selected external reference clock gnal switched to the central clock device CCG. The The direction of the check is therefore the direction of connection opposite.

The telecommunications switching system can be designed in such a way that at least some of the line sections are designed redundantly. If the line sections are checked in sections that a line section is faulty, the corresponding redundant line section is checked for the absence of faults. In the structure of the switching system shown in FIG. 2, the line section CCG-IOCC is implemented in duplicate, for example. He gives himself when checking the line section CCG - IOCC that this is disturbed, is switched to the double line section CCG * - IOCC *, which is then checked for absence of faults.

The processes described can be carried out by one of the central Control device assigned to the clock device CCG the. This can be the central control CC of the system or a separate control of the central clock device CCG. It can also be provided partial controls, one of which CCGC partial control of the central clock device CCG and white Other sub-controls IOCC, IOCG, LTUC and the interfaces are indirectly assigned to adjacent line sections.

FIG. 3 shows a central clock device CCG to which modules BG providing reference clock are connected in a switching system according to FIG. 1. The assembly BG shown as an example in FIG. 3 corresponds to the connection unit LTU4 in FIG. 1. Each assembly BG has an assembly-specific processor MPB which carries out the control processes on the respective assembly in connection with the control CCGC and a processor MPC central clock device CCG performs. Each assembly can have several sets, for example sets S _A and S _B. The set S _A can correspond to the switching device S in FIG. 2. To the sentences lead to connection lines, via the external reference clock signals, for. B. f _RA and f _{RB are} supplied. The sets are connected on the system input side to a PEB unit; at their output they are connected to a PEC unit. The units PEB and PEC are connected to the module-specific microprocessor MPB or to the microprocessor MPC of the central clock device CCG. The devices PEB and PEC, as will be described, check the supplied reference clock signals for clock errors and assign individual error values to them. These error values are individually managed in a table memory TS for each external reference clock signal.

The microprocessor MPC controls the regulation of the phase rule circle, which further consists of a phase discriminator PD, ei digital / analog converter DAC, a voltage controlled Oscillator VCO and a feedback loop FD, which the output frequency of the voltage controlled oscillator VCO leads back to an input of the phase discriminator PD.

The devices PEB and PEC determine the clock errors "clock not switchable", "bit slip", "bit error rate <10 ^-6 ", "bit error rate <10 ^-3 ", "lost frame" and "No signal". The bit error rates are determined using the CRC4 procedure according to CCITT G.704. The microprocessors MPC and MPB recognize the errors "clock not recognized", "regulation not possible" and "becomes out of sync". The corresponding procedures for the detection of these errors run in several stages: In a first stage, the control circuit of the clock device CCG classifies an existing signal for frequency and phase and checks whether it can represent an external reference clock signal depending on the frequency and phase detected. In a second stage it is checked whether the central clock device CCG can be synchronized with the present signal, which can represent an external reference clock signal, who can. In a third stage it is checked whether the clock device CCG is synchronous with the present signal.

A fault on the reference clock path, which consists in the fact that an unselected reference clock signal is supplied to the central clock device CCG, is recognized by the control CCGC in that, on the one hand, the switching states of the switching devices S ( FIG. 2) arranged in the modules providing the reference clock, and on the other hand the microprocessor MPC can be queried for the detection of a clock signal. If it is found that an external clock signal is recognized by the central clock generator when the switching device is open in the TMD41 module, this indicates that other switching devices S connected in parallel in the module supplying the reference clock are incorrectly closed. A selected external reference clock signal can only be switched on via the TMD41 module when the defect in connection with the faulty switching device (s) has been eliminated. Thus, if a fault is detected during a first check of the reference clock distance with the switching device S open, switching devices connected in parallel to the switching device S of the same reference clock supplying module are opened. Subsequently, the reference clock path is checked again for the absence of faults as part of a second check. If no faults are detected in the course of the second check, the switching device S is closed and the selected external reference clock signal is thus connected to the central clock device CCG. If, on the other hand, a malfunction is detected again as part of the second check, all records of the switching system, not just the module supplying the reference clock, are activated and the switching system is restarted.

Claims (8)

1. A method for connecting an external reference clock signal in a switching system, the switching system for synchronization of a central clock device (CCG) from external reference clock sources with at least two external reference clock signals to at least one reference clock supplying module (LTU4, TMD41) of the switching system being supplied by which exactly an external reference clock signal is selected for connection to the central clock device (CCG) and switched on, characterized in that
that a controller (CCGC) assigned to the central clock device (CCGC) connects a connecting line (LTU4 - CCG) to the connecting switch (LTU4 - CCG) between the central clock device (CCG) and an initially open switching device (S) arranged in the module providing the reference clock (LTU4, TMD41) central clock device (CCG) switches on,
that the central clock device (CCG) checks the connected connecting line (LTU4 - CCG) for the absence of faults,
that the controller (CCGC) assigned to the central clock device (CCGC) closes the switching device (S) in the module supplying the reference clock (LTU4, TMD41) in dependence on the check result in the absence of faults and thus closes the selected external reference clock signal to the central clock device (CCG) turns on. 2. The method according to claim 1, characterized, that provided the connecting line (LTU4 - CCG) from each other connectable line sections (LTU4 - IOCG; IOCG - IOCC; IOCC - CCG), the line sections (LTU4 - IOCG; IOCG - IOCC; IOCC - CCG) starting from the central clock facility (CCG) in sections in the direction of the switching device (S) in the module supplying the reference clock (LTU4, TMD41) be checked for the absence of faults in the opposite direction of the switch-off.   3. The method according to claim 2, characterized in
that the connecting line (LTU4 - CCG), starting from the first line section (CCG - IOCG) immediately adjacent to the central clock device (CCG), the line sections (LTU4 - IOCG; IOCG - IOCC; IOCC - CCG) in the manner of absence of faults is checked
that in a first procedural step the first line section (CCG - IOCG), in a second step the first line section (CCG - IOCC) together with a second line section (IOCC - IOCG) immediately adjacent to the first line section (CCG - IOCC) in the absence is checked by malfunctions,
that in any further steps that follow, a further line section (IOCG - LTU4) immediately adjacent to the line section already tested (CCG - IOCC - IOCG) is checked. 4. The method according to any one of claims 2 or 3, characterized, that at least some of the line sections (LTU4 - IOCG; IOCG - IOCC; IOCC - CCG) is designed redundantly, and that, if a line section is faulty during the check the corresponding redundant line is recognized cut is checked for absence of interference. 5. The method according to any one of the preceding claims, characterized in
that if at least one additional switching device (SB) in the reference clock supplying module (LTU4) is connected in parallel with the switching device (S, SA) and, if a fault occurs during a first check of the connecting line (LTU4 - CCG) when the switching device (S) is open is recognized, all switching devices of the module supplying the reference clock (LTU4) are opened,
that the connection line (LTU4 - CCG) is then checked again in the course of a second check for the presence of faults, and
that depending on the result of the second check in the absence of interference, the switching device (S, SA) closed and thus the selected external reference clock signal to the central clock device (CCG) is switched on. 6. The method according to claim 5, characterized, that, if again a malfunction in the second check is recognized, all sentences of the switching system, So not only the module supplying the reference clock is unlocked and the switching system is restarted. 7. Device for performing the method according to a the preceding claims, characterized, that the switching system with the central clock facility (CCG), with at least one module providing the reference clock (LTU4) and, if applicable, from line sections (LTU4 - IOCG; IOCG - IOCC; IOCC - CCG) existing connection line (LTU4 - CCG) between the central clock facility (CCG) and the in of the module providing the reference clock Switching device (S) has a controller (CCGC), the one the control program defining the method is assigned. 8. The device according to claim 6, characterized, that control by at least two partial controls det, of which a partial control (CCGC) of the central Clocking device (CCG) and further partial controls (IOCC, IOCG; LTUC) as interfaces of immediately adjacent line sections te are assigned.