DE4130637A1 - Mfg. connection element for power semiconductor module - esp. from one-side copper@ coated polyimide foil - Google Patents

Mfg. connection element for power semiconductor module - esp. from one-side copper@ coated polyimide foil

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Publication number
DE4130637A1
DE4130637A1 DE4130637A DE4130637A DE4130637A1 DE 4130637 A1 DE4130637 A1 DE 4130637A1 DE 4130637 A DE4130637 A DE 4130637A DE 4130637 A DE4130637 A DE 4130637A DE 4130637 A1 DE4130637 A1 DE 4130637A1
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DE
Germany
Prior art keywords
openings
metal layer
carrier
esp
power semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE4130637A
Other languages
German (de)
Inventor
Henning Dipl Phys Dr Oetzmann
Kurt Dipl Phys Dr Langer
Hans-Joachim Dipl Krokoszinski
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ABB Patent GmbH
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ABB Patent GmbH
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Publication date
Application filed by ABB Patent GmbH filed Critical ABB Patent GmbH
Priority to DE4130637A priority Critical patent/DE4130637A1/en
Publication of DE4130637A1 publication Critical patent/DE4130637A1/en
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0154—Polyimide
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0388—Other aspects of conductors
    • H05K2201/0394—Conductor crossing over a hole in the substrate or a gap between two separate substrate parts
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/0554—Metal used as mask for etching vias, e.g. by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0548—Masks
    • H05K2203/056—Using an artwork, i.e. a photomask for exposing photosensitive layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0073—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces
    • H05K3/0082—Masks not provided for in groups H05K3/02 - H05K3/46, e.g. for photomechanical production of patterned surfaces characterised by the exposure method of radiation-sensitive masks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3468—Applying molten solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Optics & Photonics (AREA)
  • Wire Bonding (AREA)

Abstract

A process is claimed for prodn. of an electrical connection element useful in a power semi-conductor module, the element consisting of a flexible electrically insulating substrate (esp. polyimide foil) which has an opt. structured metal (esp. copper) layer on its upper face and which has one or more openings below the metal layer. The process involves (a) producing the openings by masked photo-ablation using an UV lamp; and (b) either applying solder (e.g. by screen printing or wave soldering) or applying electrically conductive adhesive (eg. by screen printing) onto the metal layer underside exposed through the oepnings. ADVANTAGE - Prodn. of the openings (esp. large openings) is simpler and is easier to automate than prior art laser ablation processes. The connection element allows redn. in the number of connections and connection types and the number of mfg. steps when used for connecting internal wiring in power semiconductor modules.

Description

Die Erfindung bezieht sich auf ein Verfahren zur Herstel­ lung eines für elektrische Verbindungen in einem Leistungs­ halbleitermodul geeigneten Verbindungselements, das aus ei­ nem flexiblen elektrisch isolierenden Träger, insbesondere einer Polyimidfolie, besteht, der auf seiner Oberseite mit einer Metallschicht, insbesondere einer Kupferschicht, ver­ sehen ist, die zu Leiterbahnen strukturiert sein kann, wo­ bei der Träger an wenigstens einer Stelle unter der Metall­ schicht eine Öffnung aufweist.The invention relates to a method of manufacture one for electrical connections in one power suitable semiconductor module connecting element made of egg nem flexible electrically insulating carrier, in particular a polyimide film, which is on the top with a metal layer, in particular a copper layer, ver see is that can be structured into traces where in the carrier at least one place under the metal layer has an opening.

Aus IBM Technical Disclosure Bulletin 1988, Vol. 31, Nr. 6, Seite 335 bis 336 ist ein Verbindungselement bekannt, das aus einer kupferkaschierten Polyimidfolie besteht. Die Po­ lyimidfolie weist Öffnungen auf, die mit Hilfe eines Lasers hergestellt sind.From IBM Technical Disclosure Bulletin 1988, Vol. 31, No. 6, Pages 335 to 336 a connecting element is known, the consists of a copper-clad polyimide film. The butt Lyimide film has openings that are created using a laser are made.

Aus IBM Technical Disclosure Bulletin 1989, Vol. 32, Nr. 3B, Seite 1 bis 3, ist ein ähnliches Verbindungselement bekannt, das Öffnungen aufweist, die durch Ätzen herge­ stellt sind. Das Verbindungselement kann mit Hilfe einer Thermode mit metallisierten und vorbeloteten Leiterbahnen einer Leiterplatte verlötet werden.From IBM Technical Disclosure Bulletin 1989, Vol. 32, No. 3B, pages 1 to 3, is a similar connecting element known, which has openings, the Herge by etching represents are. The connecting element can with the help of a  Thermode with metallized and pre-soldered conductor tracks to be soldered to a circuit board.

Diese aus der Mikroelektronik bekannte Filmtechnik und ins­ besondere die Verfahren zur Herstellung von kupferkaschier­ ten Kunststoffolien haben keine Anwendung zur Herstellung von Verbindungselementen für Leistungshalbleitermodule ge­ funden. Es werden auch jetzt noch einzelne Kupferclips oder Dickdrahtbonds zur Herstellung von Verbindungen innerhalb von Leistungshalbleitermodulen verwendet, obwohl sie auf­ wendige Herstellverfahren erfordern. Die Herstellung der Öffnungen in kupferkaschierten Kunststoffolien ist nämlich ebenfalls aufwendig, insbesondere wenn große Öffnungen mit Hilfe eines Laserstrahls herzustellen sind.This film technology known from microelectronics and ins in particular the processes for the production of copper cladding Plastic foils have no application in manufacturing of connecting elements for power semiconductor modules ge find. There are still individual copper clips or Thick wire bonds for making connections within used by power semiconductor modules, although on Require agile manufacturing processes. The manufacture of the There are openings in copper-clad plastic films also expensive, especially when using large openings To be produced with the help of a laser beam.

Davon ausgehend liegt der Erfindung die Aufgabe zugrunde, ein verbessertes Verfahren zur Herstellung eines Verbin­ dungselements für Leistungshalbleitermodule anzugeben.Proceeding from this, the object of the invention is an improved method of making a verb Specification element for power semiconductor modules.

Diese Aufgabe wird gelöst durch ein Verfahren zur Herstel­ lung eines für elektrische Verbindungen in einem Leistungs­ halbleitermodul geeigneten Verbindungselements, das aus ei­ nem flexiblen elektrisch isolierenden Träger, insbesondere einer Polyimidfolie, besteht, der auf seiner Oberseite mit einer Metallschicht, insbesondere einer Kupferschicht, ver­ sehen ist, die zu Leiterbahnen strukturiert sein kann, wo­ bei der Träger an wenigstens einer Stelle unter der Metall­ schicht eine Öffnung aufweist, und wobeiThis problem is solved by a manufacturing process one for electrical connections in one power suitable semiconductor module connecting element made of egg nem flexible electrically insulating carrier, in particular a polyimide film, which is on the top with a metal layer, in particular a copper layer, ver see is that can be structured into traces where in the carrier at least one place under the metal layer has an opening, and wherein

  • a) die Öffnungen im Träger durch maskierte Photoablation unter Verwendung einer UV-Lampe hergestellt werden, unda) the openings in the carrier by masked photoablation be made using a UV lamp and
  • b) die Metallschicht auf ihrer Unterseite in den durch Öffnungen im Träger freigegelegten Bereichen durch Aufbringen von Lot, z. B. im Siebdruckverfahren oder durch Wellenlöten, vorbelotet wird.b) the metal layer on its underside in the through Openings in the exposed areas through  Applying solder, e.g. B. in the screen printing process or by wave soldering.

Außerdem wird die Aufgabe durch ein Verfahren gelöst, das sich vom vorstehenden Verfahren dadurch unterscheidet, daß keine Vorbelotung der Metallschicht vorgenommen wird, son­ dern ein elektrisch leitfähiger Kleber auf die freigelegten Metallschichten, z. B. im Siebdruckverfahren, aufgetragen wird.In addition, the problem is solved by a method that differs from the above method in that no pre-soldering of the metal layer is carried out, son an electrically conductive glue on the exposed Metal layers, e.g. B. applied by screen printing becomes.

Die beiden Verfahrensvarianten ermöglichen die Bereitstel­ lung von Verbindungselementen zur Kontaktierung von Lei­ stungshalbleiterchips mit lötfähigen Kontaktflächen bzw. von Leistungshalbleiterchips mit nichtlötfähigen, d. h. Alu­ miniumkontakten.The two process variants enable readiness development of connecting elements for contacting lei circuit semiconductor chips with solderable contact areas or of power semiconductor chips with non-solderable, d. H. Alu minium contacts.

Die erfindungsgemäße Verwendung einer UV-Lampe anstelle ei­ nes Laserstrahlers hat den Vorteil, daß durch die praktisch gleichmäßige Beleuchtung einer großen Fläche eine wesentli­ che Beschleunigung und Erleichterung des Photo-Ablations­ prozesses erzielt wird. Damit wird z. B. ein bei Laserbe­ strahlung übliches mechanisches, schrittweises Verschieben eines Verbindungselements überflüssig, weil das gesamte Element gleichzeitig bestrahlt wird. Die Herstellung von Verbindungselementen wird dadurch wesentlich vereinfacht und kann problemlos automatisiert werden.The inventive use of a UV lamp instead of egg Nes laser emitter has the advantage that through the practical uniform lighting of a large area is an essential Accelerating and facilitating photo ablation process is achieved. So that z. B. at Laserbe radiation usual mechanical, gradual shifting of a fastener unnecessary because the whole Element is irradiated simultaneously. The production of Fastening elements are thereby considerably simplified and can be automated easily.

Die Verbindungselemente mit einer Lot- oder Kleberbeschich­ tung können in einer automatisierten Modulfertigung einge­ setzt werden. Sie ermöglichen auch auf einfache Weise eine Integration von Mikroelektronikschaltungen in Leistungs­ elektronikgruppen, also die sogenannte Vorwärts-Integra­ tion. The connecting elements with a solder or adhesive coating can be used in automated module production be set. They also enable one in a simple manner Integration of microelectronic circuits in power electronics groups, the so-called forward integra tion.  

Die zur Herstellung des Verbindungselements verwendete UV-Lampe muß selbstverständlich eine hinreichende Lei­ stungsdichte aufweisen. Geeignete UV-Lampen sind in dem Aufsatz "Neue UV-Strahler für industrielle Anwendungen", ABB Technik 3/91, Seite 21 bis 28 beschrieben.The one used to make the connector UV lamp must of course have sufficient lei exhibit density. Suitable UV lamps are in the Article "New UV lamps for industrial applications", ABB Review 3/91, pages 21 to 28.

Die Erfindung und weitere Vorteile werden nachstehend an­ hand von in der Zeichnung dargestellten Ausführungsbeispie­ len näher erläutert. Es zeigen dieThe invention and further advantages are set out below hand from execution example shown in the drawing len explained in more detail. They show

Fig. 1a bis 1e das erfindungsgemäße Verfahren zur Her­ stellung eines Verbindungselements, FIG. 1a to 1e, the inventive method for the manufacture position of a connecting element,

Fig. 2 Modulanordnung mit einer weiteren Ver­ drahtungsebene für einen Steuerteil. Fig. 2 module arrangement with another Ver wiring level for a control part.

Fig. 1a zeigt ein bevorzugtes Ausgangsmaterial, nämlich eine kupferkaschierte Polyimidfolie 1, die kommerziell als Kapton-Folie sowohl mit unterschiedlichen Dicken des elek­ trisch isolierenden Trägers 2, also des Polyimids, als auch verschiedenen Dicken der Metallschicht 3 aus Kupfer erhält­ lich ist. Die Folie 1 wird in große, aber noch bequem pro­ zessierbare Stücke von beispielsweise 4′′×6′′ geschnitten. Die Erfindung läßt sich jedoch auch mit anderem Ausgangsma­ terial realisieren. Fig. 1a shows a preferred starting material, namely a copper-clad polyimide film 1 , which is commercially available as a Kapton film both with different thicknesses of the electrically insulating support 2 , that is, the polyimide, and various thicknesses of the metal layer 3 made of copper. The film 1 is cut into large, but still conveniently per zessbare pieces of, for example, 4 '' × 6 ''. However, the invention can also be realized with a different material.

Fig. 1b zeigt eine Folie 1 nach einer photolitografischen Strukturierung der Kupferschicht 3 zur Herstellung ge­ wünschter Leiterbahnen. Diese Strukturierung kann nach ei­ nem bekannten Verfahren durch Belacken, Belichten, Ent­ wickeln, Ätzen und Lackstrippen erfolgen. Fig. 1b shows a film 1 after a photolithographic structuring of the copper layer 3 for the production of ge desired conductor tracks. This structuring can be carried out according to a known method by coating, exposure, developing, etching and lacquer stripping.

Fig. 1c zeigt einen für die Erfindung wesentlichen Schritt, nämlich das Herstellen von Öffnungen 4 (siehe Fi­ gur 1d) in der unter der Kupferschicht 3 befindlichen Poly­ imidfolie 2. Die Öffnungen 4, also die Kontaktlöcher, wer­ den durch maskierte Photo-Ablation hergestellt. Dabei wird eine Metallmaske 5 benutzt, die einfach hergestellt werden kann und durch deren Austausch auf einfache Weise eine An­ passung an ein geändertes Layout möglich ist. Das Photo-Ablationsverfahren ist z. B. in "Photoablation of Po­ lyimid with IR and UV Laser Radiation", Applied Surface Science 43 (1989), Seite 352 bis 357, North Holland, be­ schrieben. Beim erfindungsgemäßen Verfahren wird die Poly­ imidfolie 2 durch Löcher 6 in der Metallmaske 5 mit Hilfe einer UV-Lampe 7 bestrahlt, das die Bindungen des Polyimids aufbricht und das Material lokal entfernt.1c shows an essential step for the invention, namely the production of openings 4 (see FIG. 1d) in the polyimide foil 2 located under the copper layer 3 . The openings 4 , ie the contact holes, who made the masked photo-ablation. In this case, a metal mask 5 is used, which can be easily manufactured and which can be easily adapted to a changed layout by being replaced. The photo ablation process is e.g. B. in "Photoablation of Polyimide with IR and UV Laser Radiation", Applied Surface Science 43 (1989), pages 352 to 357, North Holland, be written. In the method according to the invention, the polyimide film 2 is irradiated through holes 6 in the metal mask 5 with the aid of a UV lamp 7 , which breaks the bonds of the polyimide and removes the material locally.

Fig. 1d zeigt ein Verbindungselement 8 nach Abschluß des in Fig. 1c gezeigten Fertigungsschrittes. Fig. 1d shows a connecting element 8 after completion of the manufacturing step shown in Fig. 1c.

Zur Vorbereitung des Verbindungselements 8 für die Montage in einem Leistungshalbleitermodul schließt sich ein in Fi­ gur 1e dargestellter Herstellungsschritt an, in welchem eine Belotung der Kupferschicht 2 von ihrer Unterseite her erfolgt. Diese Belotung wird z. B. mit Hilfe einer Wellenlötanlage durchgeführt, wobei alle durch Photo-Ablation freigegebenen Kupferflächen mit einem z. B. niedrig schmelzenden Lot 8 benetzt werden. Der Polyi­ mid-Rand der Flächen dient dabei als Lötstopp. Die herge­ stellte Lotdicke kann durch die Prozeßparameter, z. B. die Durchlaufgeschwindigkeit, eingestellt werden. Durch diese Vorbelotung entfällt auf vorteilhafte Weise die Notwendig­ keit auf Halbleiter-Chips, die mit Hilfe des Verbindungs­ elements 8 kontaktiert werden sollen, sogenannte Bumps her­ zustellen. Die Halbleiter-Chips und andere Bauelemente müs­ sen lediglich lötbare Kontakte aufweisen. To prepare the connecting element 8 for mounting in a power semiconductor module, a manufacturing step shown in FIG. 1 e follows, in which the copper layer 2 is soldered from its underside. This brazing is z. B. performed with the help of a wave soldering system, all copper surfaces released by photo-ablation with a z. B. low melting solder 8 are wetted. The polyimide edge of the surfaces serves as a solder stop. The solder thickness produced can be determined by the process parameters, e.g. B. the throughput speed can be set. This preliminary soldering advantageously eliminates the need for semiconductor chips that are to be contacted with the aid of the connecting element 8 , so-called bumps. The semiconductor chips and other components only have to have solderable contacts.

Soweit das in Fig. 1d gezeigte Element noch nicht das ge­ wünschte einzelne Verbindungselement 8 ist, sondern noch eine Folie mit mehreren zusammenhängenden Verbindungsele­ menten, so schließt sich noch ein Stanzschritt zur Teilung in einzelne Verbindungselemente 8 an.As far as the element shown in FIG. 1d is not yet the desired individual connecting element 8 , but is still a film with several connected connecting elements, a punching step for division into individual connecting elements 8 follows.

Anstelle einer Vorbelotung, die auch vorteilhaft im Sieb­ druckverfahren aufgebracht werden kann, kann auch eine Be­ schichtung mit einem Leitkleber z. B. im Siebdruckverfahren durchgeführt werden.Instead of a preliminary brazing, which is also advantageous in the sieve printing process can be applied, a loading layering with a conductive adhesive e.g. B. in the screen printing process be performed.

Fig. 2 zeigt in einer schematischen Darstellung ein Ver­ wendungsbeispiel für Verbindungselemente 8, wobei in einem Leistungshalbleitermodul eine weitere Verdrahtungsebene für Steuereinrichtungen 20 vorgesehen ist. Die Halterung einer dafür geeigneten Trägeranordnung 21 im Gehäuse eines Moduls ist nicht dargestellt. Der Fig. 2 ist zu entnehmen, daß zur Herstellung elektrischer Verbindungen zwischen der zweiten und der dritten Verdrahtungsebene ebenfalls Folien­ clips nach der Art des Verbindungselements 8 eingesetzt werden. Auf diese Weise können separat gefertigte und gete­ stete Steuerungsteile auf einfache Weise durch Hochbiegen eines Verbindungselements 8 nachträglich mit einem geteste­ ten Leistungsteil eines Moduls kombiniert werden. In Modu­ len kleiner Leistung können außerdem Verbindungselemente 8 anstelle von Anschlußlaschen 18 eingesetzt werden. Fig. 2 shows a schematic view of an application example Ver for fasteners 8, wherein an additional wiring level for control means 20 is provided in a power semiconductor module. The mounting of a suitable carrier arrangement 21 in the housing of a module is not shown. Fig. 2 can be seen that for making electrical connections between the second and third wiring level also film clips are used in the manner of the connecting element 8 . In this way, separately manufactured and continuous control parts can be easily combined with a tested power part of a module by bending a connecting element 8 . In Modu len small power fasteners 8 can also be used instead of connecting tabs 18 .

Durch die Verwendung des erfindungsgemäßen Verbindungsele­ ments 8 für die interne Verdrahtung in Leistungshalbleiter­ modulen wird im Vergleich zu Anordnungen und Herstellver­ fahren nach dem Stand der Technik erreicht, daß die Anzahl der Verbindungen und der Verbindungstypen im Modul und da­ mit auch die Zahl der notwendigen Fertigungsschritte erheb­ lich kleiner wird.Through the use of the connecting element 8 according to the invention for internal wiring in power semiconductor modules, compared to arrangements and manufacturing processes according to the prior art, the number of connections and the connection types in the module and thus also the number of necessary manufacturing steps is increased gets smaller.

BezugszeichenlisteReference symbol list

 1 kupferkaschierte Polyimidfolie
 2 elektrisch isolierender Träger, z. B. Polyimidfolie
 3 Metallschicht, z. B. Kupferschicht
 4 Öffnungen am Träger
 5 Metallmaske
 6 Loch
 7 UV-Licht
 8 Verbindungselement
 9 Lot
10 Substrat
11 strukturierte Metallisierung
12 Bauelement
18 Anschlußlasche
20 Steuerungseinrichtung
21 Trägeranordnung 1 copper-clad polyimide foil
2 electrically insulating supports, e.g. B. polyimide film
3 metal layer, e.g. B. copper layer
4 openings on the support
5 metal mask
6 holes
7 UV light
8 connecting element
9 lot
10 substrate
11 structured metallization
12 component
18 connecting strap
20 control device
21 carrier arrangement

Claims (2)

1. Verfahren zur Herstellung eines für elektrische Verbin­ dungen in einem Leistungshalbleitermodul geeigneten Verbin­ dungselements, das aus einem flexiblen elektrisch isolie­ renden Träger, insbesondere einer Polyimidfolie besteht, der auf seiner Oberseite mit einer Metallschicht, insbeson­ dere einer Kupferschicht, versehen ist, die zu Leiterbahnen strukturiert sein kann, wobei der Träger an wenigstens ei­ ner Stelle unter der Metallschicht eine Öffnung aufweist, dadurch gekennzeichnet, daß
  • a) die Öffnungen im Träger durch maskierte Photoablation unter Verwendung einer UV-Lampe hergestellt werden, und
  • b) die Metallschicht auf ihrer Unterseite in den durch Öffnungen im Träger freigegelegten Bereichen durch Aufbringen von Lot, z. B. im Siebdruckverfahren oder durch Wellenlöten, vorbelotet wird.
1. A method for producing a suitable for electrical connec tions in a power semiconductor module connec tion element, which consists of a flexible electrically insulating support, in particular a polyimide film, which is provided on its top with a metal layer, in particular a copper layer, which leads to conductor tracks can be structured, the carrier having an opening at least at one point beneath the metal layer, characterized in that
  • a) the openings in the carrier are produced by masked photoablation using a UV lamp, and
  • b) the metal layer on its underside in the areas exposed by openings in the carrier by applying solder, z. B. is pre-soldered in the screen printing process or by wave soldering.
2. Verfahren zur Herstellung eines für elektrische Verbindungen in einem Leistungshalbleitermodul geeigneten Verbindungselements, das aus einem flexiblen elektrisch isolierenden Träger, insbesondere einer Polyimidfolie be­ steht, der auf seiner Oberseite mit einer Metallschicht, insbesondere einer Kupferschicht, versehen ist, die zu Lei­ terbahnen strukturiert sein kann, wobei der Träger an we­ nigstens einer Stelle unter der Metallschicht eine Öffnung aufweist, dadurch gekennzeichnet, daß
  • a) die Öffnungen im Träger durch maskierte Photoablation unter Verwendung einer UV-Lampe hergestellt werden, und
  • b) die Metallschicht auf ihrer Unterseite in den durch Öffnungen im Träger freigegelegten Bereichen mit ei­ nem elektrisch leitenden Kleber z. B. im Sieb-druck­ verfahren beschichtet wird.
2. A method for producing a suitable connecting element for electrical connections in a power semiconductor module, which consists of a flexible electrically insulating carrier, in particular a polyimide film, which is provided on its top with a metal layer, in particular a copper layer, which are structured to conductors can, wherein the carrier at least at least one point under the metal layer has an opening, characterized in that
  • a) the openings in the carrier are produced by masked photoablation using a UV lamp, and
  • b) the metal layer on its underside in the areas exposed by openings in the carrier with egg nem electrically conductive adhesive z. B. coated in screen printing process.
DE4130637A 1990-10-11 1991-09-14 Mfg. connection element for power semiconductor module - esp. from one-side copper@ coated polyimide foil Ceased DE4130637A1 (en)

Priority Applications (1)

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DE4130637A DE4130637A1 (en) 1990-10-11 1991-09-14 Mfg. connection element for power semiconductor module - esp. from one-side copper@ coated polyimide foil

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Application Number Priority Date Filing Date Title
DE4032272 1990-10-11
DE4130637A DE4130637A1 (en) 1990-10-11 1991-09-14 Mfg. connection element for power semiconductor module - esp. from one-side copper@ coated polyimide foil

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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4300516A1 (en) * 1993-01-12 1994-07-14 Abb Ixys Semiconductor Gmbh Power semiconductor module with insulating substrate
DE19508835C1 (en) * 1995-03-11 1996-04-25 Freudenberg Carl Fa Making blind holes in double-sided circuit boards for through-hole connection
DE19621545C1 (en) * 1996-05-29 1998-02-05 Cicorel S A Production of circuit board
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
WO2004038471A1 (en) * 2002-10-28 2004-05-06 Terahertz Photonics Ltd An optical board with electrical and optical wiring layers and a method of its production
DE10355925A1 (en) * 2003-11-29 2005-06-30 Semikron Elektronik Gmbh Power semiconductor module and method of its manufacture
DE102006013078A1 (en) * 2006-03-22 2007-10-04 Semikron Elektronik Gmbh & Co. Kg Compact power semiconductor module with connection device
DE102018206482A1 (en) * 2018-04-26 2019-10-31 Infineon Technologies Ag Semiconductor device with a clip made of composite material
DE102019218417A1 (en) * 2019-11-28 2021-06-02 Heraeus Deutschland GmbH & Co. KG Process for the production of a substrate equipped with one or more solder depots

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DE4004602A1 (en) * 1990-02-15 1991-08-29 Asea Brown Boveri METHOD FOR PRELIMINATING A SUBSTRATE

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Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4300516A1 (en) * 1993-01-12 1994-07-14 Abb Ixys Semiconductor Gmbh Power semiconductor module with insulating substrate
DE4300516C2 (en) * 1993-01-12 2001-05-17 Ixys Semiconductor Gmbh Power semiconductor module
DE19508835C1 (en) * 1995-03-11 1996-04-25 Freudenberg Carl Fa Making blind holes in double-sided circuit boards for through-hole connection
US5842273A (en) * 1996-01-26 1998-12-01 Hewlett-Packard Company Method of forming electrical interconnects using isotropic conductive adhesives and connections formed thereby
DE19621545C1 (en) * 1996-05-29 1998-02-05 Cicorel S A Production of circuit board
WO2004038471A1 (en) * 2002-10-28 2004-05-06 Terahertz Photonics Ltd An optical board with electrical and optical wiring layers and a method of its production
DE10355925B4 (en) * 2003-11-29 2006-07-06 Semikron Elektronik Gmbh & Co. Kg Power semiconductor module and method of its manufacture
US7042074B2 (en) 2003-11-29 2006-05-09 Semikron Elektronik Gmbh & Co., Kg Power semiconductor module and method for producing it
DE10355925A1 (en) * 2003-11-29 2005-06-30 Semikron Elektronik Gmbh Power semiconductor module and method of its manufacture
DE102006013078A1 (en) * 2006-03-22 2007-10-04 Semikron Elektronik Gmbh & Co. Kg Compact power semiconductor module with connection device
DE102006013078B4 (en) * 2006-03-22 2008-01-03 Semikron Elektronik Gmbh & Co. Kg Compact power semiconductor module with connection device
US7626256B2 (en) 2006-03-22 2009-12-01 Semikron Elektronik Gmbh & Co. Kg Compact power semiconductor module having a connecting device
DE102018206482A1 (en) * 2018-04-26 2019-10-31 Infineon Technologies Ag Semiconductor device with a clip made of composite material
US10971457B2 (en) 2018-04-26 2021-04-06 Infineon Technologies Ag Semiconductor device comprising a composite material clip
DE102018206482B4 (en) 2018-04-26 2024-01-25 Infineon Technologies Ag Semiconductor component with a composite clip made of composite material
DE102019218417A1 (en) * 2019-11-28 2021-06-02 Heraeus Deutschland GmbH & Co. KG Process for the production of a substrate equipped with one or more solder depots

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