DE4123356C2 - Semiconductor arrangement for a level shifter in I · 2 · L technology - Google Patents

Description

The invention relates to an arrangement according to the preamble of claim 1, such as it is known from DE 27 50 432 C2.

In I ² L technology, the logic gates for converting the input signal are implemented using NPN switching transistors; Each vertical NPN switching transistor is linked to a lateral PNP injection transistor operating as a current source, which represents the active load at the input or output of the gate. The individual gates are connected to one another by interconnects and the output signals which are present at the collectors of the switching transistors are logically linked to one another by means of this wiring (“WIRED AND”). The number of outputs per gate can be increased by using switching transistors with multiple collectors. Logic arrangements in I ² L technology can be built up in a very space-saving manner by the functional integration - the collector of the lateral injection transistor is also the basis of the vertical switching transistor. In the case of integrated circuits, some of which are constructed with circuit components in I ² L technology, signals from I ² L circuit parts (supply voltage approx. 25 V) often have to be decoupled and transmitted to other, potentially lower, circuit parts.

For this purpose, level shifters ("level shifters" or "cur rent hoggers") are used: FIG. 1 shows the principle circuit diagram, FIG. 2 shows a top view and FIG ² L technology (internal state of the art). Referring to FIG. 1, the collector is C ₁ of the PNP injection transistor T ₁ is connected to the emitter E ₂ of the PNP output coupling transistor T _2; the collector C _{2 of} the transistor T ₂ forms the output of the level shifter. According to Fig. 2 and 3, the two transistors T ₁ and T ₂ have as respective base region B _1, B ₂ a common N-well 2, 5, in which the P⁺-regions 1, 3, 4 and 6 for the emitter E _{1 of} the transistor T ₁ (this is the so-called injector), the collector C _{1 of} the transistor T ₁ , the emitter E _{2 of} the transistor T ₂ and the collector C _{2 of} the transistor T _{2 are} embedded. The entire structure is separated from adjacent logic gates or components by an N⁺ isolation zone 7 ; with the reference numeral 8 , the (N⁺-doped) substrate is also shown in FIG. 3.

Due to a too small distance between the isolation zone 7 and the P⁺ region 6 of the collector C _{2 of} the lateral PNP transistor T ₂ - the limit 9 of the N⁺-Ge region 7 can be due to thermal effects or diffusion processes into the P⁺ area 6 he stretch (dashed line 10 ) - is a - shown in Fig. 3 - parasitic Zener diode Z. This limits the area of application of the level shifter, since the voltage can only shift to a lower potential, at which the Zener voltage has not yet been reached - this voltage is usually 3-4 V.

The invention has for its object a verbes serter level shifters with a larger range of applications give.

This object is achieved by the features solved in the characterizing part of claim 1.

The objective features of claim 1 are indeed in the known from DE 27 50 432 C2 Arrangement before, however, this is called a logic gate and not used as a level shifter.

Advantageous further developments of the invention result from the subclaims.

An intermediate layer is introduced between the isolation zone and the collector zone of the second transistor. As shown in the semiconductor arrangement or the layout in plan view ( FIG. 4) and in section ( FIG. 5), the intermediate layer 11 can be realized in example that the distance between the N⁺ insulation zone 7 and the P⁺ Area 6 of the collector C _{2 of} the transistor T _{2 is} increased; the boundary layer 9 of the N⁺ region 7 (or the shifted due to thermal processes or diffusion effects boundary layer 10 ), the P⁺ region 6 of the collector C _{2 of} the transistor T ₂ can no longer reach, so that a partial area of the two base regions 2 , 5 form the low-doped N zone with the extent d between the N⁺ region of the isolation zone 7 and the P⁺ region 6 of the collector C ₂ remains. So that the intermediate layer 11 remains even under unfavorable conditions, its minimum expansion should be 20-30 µm. The presence of the intermediate layer prevents the formation of the parasitic zener diode mentioned above - as a result, the voltage can be shifted to a potential which is only limited by the technology used or by the maximum reverse voltage of the PNP transistor T ₂ .

The maximum voltage range or area of application the level shifter is therefore no longer affected by the Circuit arrangement, but only by the limit values of the technology used, so that one a level shifter with a much larger insert get rich.

Claims (3)

1. Semiconductor arrangement in I ² L technology, with a first PNP transistor (T ₁ ) as an injection transistor and a second PNP transistor (T ₂ ) as a coupling-out transistor, the emitter (E ₁ ) and the collector (C ₁ ) of the first transistor (T ₁ ) and the emitter (E ₂ ) and the collector (C ₂ ) of the second transistor (T ₂ ) as highly doped P⁺ regions ( 1 , 3 , 4 , 6 ) in an N-doped region ( 2nd , 5 ), which forms the bases (B ₁ , B ₂ ) of the two transistors (T ₁ , T ₂ ), are embedded, the highly doped P⁺ region forming the collector (C ₂ ) of the second transistor (T ₂ ) ( 6 ) is separated from adjacent components or logic gates by a heavily doped N⁺ isolation zone ( 7 ), and wherein between the heavily doped N⁺ isolation zone ( 7 ) and the P⁺-doped collector region ( 6 ) of the second transistor ( T ₂ ) an intermediate layer ( 11 ) made of N-conducting material is arranged, characterized in that the semiconductor arrangement as a level Chieber is used and for this purpose the intermediate layer ( 11 ) has such a width (d) that its edge layer ( 9 ) does not have the P⁺-doped collector region ( 6 ) of the second transistor (T₂) even when thermal effects or diffusion processes occur reached. 2. Semiconductor arrangement according to claim 1, characterized in that the intermediate layer ( 11 ) consists of a portion of the bases (B ₁ , B ₂ ) of the two transistors (T ₁ , T ₂ ) forming the H region ( 2 , 5 ). 3. Semiconductor arrangement according to claim 1 or 2, characterized in that the extent (d) of the intermediate layer ( 11 ) is at least 20-30 microns.