DE4111733C1 - Universal symmetrising method for current distribution in parallel three=phase inverters - controlling pulse formation w.r.t. shunt or zero current thresholds by supplying corresp. null vectors - Google Patents

Abstract

The universal regulating system is for current symmetry within parallel inverters (WRA,WEB) supplying an electric drive. A control device (1) provides setting signals (SW,SV,SU) fed to pulse former stages (3UA,3UB) for controlling switching of the inverters (WRA,WRB). The individual currents at the outputs of the inverters (WRA,WRB) are detected by current converters (8UA,8WB) and fed to comparators (6). The outputs of all 3 comparators are summated and divided by 3 to provide a zero current (iqo). This is compared with the comparator outputs (iqu,iqv,iqw) to provide shunt currents fed to an auxiliary control device (2) between the main control device (1) and the pulse former stages (3UA,3UB). ADVANTAGE - Prevents asymmetrical loading of power semiconductors. Does not require selection of power semiconductor or manipulation switching characteristics of shunt coils.

Description

The invention relates to a method according to the preamble of claim 1. Such a method is through the IEEE transactions on Industry Applications, Vol. Ia-19, No. 2, March / April 1983, pages 198 to 205 known.

Three-phase inverters, in particular three-phase pulse inverters, find wide applications, for example in three-phase drives and uninterruptible power supply systems. In one application for higher outputs, the inverters may be connected in parallel unavoidable if the current capacity of the available power semiconductors is not sufficient.

Fig. 2 shows a typical parallel connection of two three-phase inverters WRA and WRB with a common DC intermediate circuit, which is shown here as Spanungsquelle U _d. The inverters WRA and WRB are constructed in the same way from power semiconductor switches TA 1 to TA 6 and TB 1 to TB 6 designed here as IGBT elements, each with free-wheeling diodes connected in antiparallel (not specified). The two inverters are connected to a three-phase _load M, for example a three-phase motor, via three decoupling _reactors L _qU , L _qV , L _qW .

Both inverters WRA and WRB have a common control device 1 , which supplies three potential setting commands SU, SV and SW (each for the voltage + U _d or the voltage 0 volt) for the three inverter strings of the two inverters. With the help of functional units 3 UA. . . 3 WB (only 3 UA and 3 UB shown), which are used here for pulse formation, become switching signals for the individual power semiconductor switches (for example TA 1 and TA 4 for the branch pair bridge UA in the inverter WRA) taking into account the delay times of the semiconductor components required for operation educated. Not shown with 4 A 1 :. . . 4 A 6 ) and 4 B 1 (not shown:... 4 B 6 ) are units which represent pulse amplifiers which are required for the amplification of the individual control signals between the control part and the power part. Although the two inverters WRA, WRB are controlled together, in practice there are usually differences in the inverter phase currents (i _UA i _UB , i _VA i _VB and i _WA i _WB ), which are asymmetrical due to the cross currents occurring as the difference between the unequal inverter phase currents Lead loads on the power semiconductor switch. The asymmetrical distribution of the currents can have the following reasons:

• - different forward voltages of the power semiconductor switches,
• Different switching and / or delay times of the power semiconductor switches, the pulse formation and the pulse amplifier,
• - Different junction temperatures of the power semiconductor switches due to the asymmetrical load or cooling.

The following measures can be taken to symmetrize the distribution of the currents to be hit:

• - Preselection of the power semiconductor switch, so that only Semiconductors with similar pass and switching behavior used will. Preselection involves additional effort connected and is therefore in practice for manufacturing and storage disadvantageous.
• - The decoupling _chokes (L _qU , L _qV and L _qW ) are used to reduce the differences in the currents. A more uniform current distribution by precalculating the required voltage time area of the cross reactors is described in the literature reference mentioned at the beginning from the "IEEE Transactions". However, this calculation requires precise knowledge of the scatter limits of the switching delay times, the forward voltages of the power semiconductor switches and their load and temperature dependency.
• - By different voltage controls of the two inverters the differences in the currents are reduced (DE 36 02 496 C2). However, this method is very complex and requires special regulations for the inverters.

The invention has for its object a method of the beginning Specify the type with which a preselection of the power semiconductor switch can be avoided without manipulation on the transverse chokes or within the operationally provided Control units is necessary.

This object is achieved according to the invention by those characterized in claim 1 Features solved.

The redundant possible switching states are advantageous the zero pointer is used to cross currents and zero current regulate without distorting the output voltage of the converter becomes. The current distribution can be independent of the spread of the Characteristic curves of the power semiconductor switches and the control units be symmetrized. It is easily possible with the procedure specified cross flow control as an additional component a parallel connection of existing devices without the Modify existing control devices or power units have to. Cross-flow control can also be used with any control method (Space vector modulation, sine-triangle comparison... Etc.) can be used.

Advantageous embodiments of the method according to the invention and  Arrangements for performing the method are in the further claims featured.

The provided asymmetrical comparator limit values (positive / negative Cross current limit and reduced zero current limit can significantly reduce the frequency of intervention of the cross flow control, so that no significant increase in the switching frequency of the Power semiconductors are created.

The invention is intended to be used in the following with the aid of an example are explained. It shows

Fig. 1 shows an arrangement for performing the method according to the invention in addition to the arrangement shown in Fig. 1,

Fig. 3 shows the switching hysteresis of the assembly of FIG. 1 and FIG. 4 crossflow used and zero-current limit comparators and

Fig. 5, the switching states of parallel-connected inverters in space vector representation.

In Fig. 1 a block diagram is shown with a cross-flow scheme 9, which operates according to the inventive method. The function of the cross flow control 9 is shown using the example of line U. First, the individual currents at the outputs of the two inverters WRA and WRB, namely the currents i _UA to i _WB, are detected by current transformers 8 UA to 8 WB and are fed to comparator elements 6 in each case in strings. The outputs of the three comparators 6 are guided to a summing element 7, whose output signal is divided into three parts in a dividing element 8, so that is in the system due to the gemeisamen intermediate circuits U of the inverter WRA and WRB _d flowing zero current i _q0 formed. This zero current i _q0 is fed to further comparison _elements 10 , to which the output _{signals of} the comparison _elements 6 i _qu , i _qv and i _qw are also applied. At the output of the comparison elements 10 , the cross currents i _{QU of} the line U and (not shown further) the cross currents of the lines V and W can be removed.

These cross currents, here for example i _QU , are each fed to two cross current limit value comparators, for the line U labeled 50 PU, 50 NU. The one cross-current limit value comparator 50 PU emits a limit value signal SUP when the cross current i _QU exceeds a positive limit value. The other cross-current limit comparator 50 NU outputs a limit signal SUN when the cross current i _{QU falls} below a negative limit. The output signals of the cross-current limit value comparators are fed to an additional control device 2 connected between the control device 1 and the pulse forming devices 3 UA, 3 UB etc.

The signal i _q₀ at the output of the divider 8 is also connected to two zero current limit comparators 50 PO, 50 NO, of which the zero current limit comparator 50 PO outputs a signal SP to the additional switching device 2 when the zero current i _{q0 has} a positive zero current - Limit value exceeds, while the further zero current limit value comparator 50 NO outputs an output signal SN to the additional control device 2 when the zero current i _{q0 falls below} a negative limit value.

Usually, the control signals 1 emitted by the control device 1 , SW, SV, SU, after distribution by the pulse-forming devices 3 UA, 3 UB, etc., characterize the switching states of the inverters at their terminal outputs, which are shown in a room pointer representation for the two inverters WRA, WRB in the order of Terminals UVA (A) / UVW (B) can be coded. Such a space pointer representation is shown in FIG. 5. The coding means
1 = output terminal connected to the pulse pole of the feeding DC voltage,
0 = output terminal connected to the negative pole of the DC supply.

The active pointers (voltage at the output terminals U, V, W) are accordingly formed by the following switching states: 110/110; 010/010; 011/011; 001/001; 101/101 and 100/100.

For the zero pointer (zero voltage at the output terminals U, V, W) 10 redundant switching states possible. At the output terminals U, V, W the voltage is zero if

• a) all three strings of the inverters WRA and WRB to the positive pole are switched (111/111),
• b) all three strings of the inverters WRA and WRB to the negative pole are switched (000/000),
• c) all three strings of the inverter WRA at the positive pole and all three strings of the inverter WRB at the negative pole or vice versa are switched (111/000) or (000/111),
• d) the strings of the inverters WRA and WRB switched complementarily are, e.g. B. 110/001 etc.

The invention makes use of the knowledge that the redundant switching states of the zero pointers can be used to regulate the cross currents (and the additionally occurring zero currents) without the output voltage of the inverters being distorted. The switching states of the zero pointers 000/000 or 111/111 are the normal switching states that are output by the control unit 1 . With them it is neither possible to influence one of the cross currents nor to influence the zero current. These switching states are forwarded by the additional control device 2 in the arrangement shown in FIG. 1 when the zero current i _q0 and the cross currents i _QU , i _QV and i _{QW are} within the tolerance _limits .

For example, if the zero current i _{q0 exceeds} the current limit I _{G of} the zero current limit comparator 50 PO, the output signal SP is raised to an H level. Now the additional control device 2 waits until one of the normal zero pointers 000/000 or 111/111 is output by the control unit 1 and then switches instead one of the redundant zero pointers, which brings the zero current i _{q0 back} below the tolerance _limit . In this case it is the zero pointer with switch position 000/111 that drives the zero current back. This zero pointer corresponding to switch position 000/111 is switched on until the zero current i _{q0 reaches} a negative tolerance limit -I _G + ΔI. The zero current limit value comparator 50 PO then switches its signal SP to L level. This ends the control process. In the future, the additional control device 2 will forward the zero pointer (000/000) or (111/111) output by the control unit 1 .

If the control device 1 specifies an active pointer during the previously described control of the zero current before the zero current i _{q0 has reached} the limit -I _G + ΔI, the control process is ended prematurely and the active pointer is forwarded by the additional control device. The regulation waits until a normal zero pointer (000/000) or (111/111) is again output by the control device 1 and then immediately starts the regulation of the zero current i _q0 again. Thus, the output voltage of the inverters WRA, WRB is not influenced by the cross-current control device 9 .

If, for example, the zero current i _{q0 exceeds} the negative tolerance limit of the further limit value _comparator 50 NO, it switches its output signal SN to the H level. The additional control device 2 then waits until one of the normal zero pointers 000/000 or 111/111 is to be output, and instead switches the redundant zero pointer with the switch position 111/000 until the logic signal SN drops again to the L level or turns on active pointer is output by the control device 1 . (An active pointer is always forwarded with priority.) If, for example, the cross _current i _{qU exceeds} the current limit I _G of the limit value comparator 50 PU that monitors the positive cross current limit, the logic signal SUP is switched to H level at its output. Now the additional control device 2 waits until one of the normal zero pointers 000/000 or 111/111 is output by the control device 1 and then switches the redundant zero pointer with the switching position 011/100 instead until the cross current i _QU a negative limit - I _G + ΔI has reached or an active pointer is output by the control device 1 .

If the cross current I _QU exceeds the negative tolerance limit -I _G of the limit value comparator 50 NU monitoring the negative limit value for the cross current, its output logic signal SUN is switched to H level. The additional control device 2 now switches the redundant zero pointer 100/011 instead of one of the normal zero pointers output by the control device 1 with the switching position 000/000 or 111/111 until the cross current i _{QU has reached} a reduced positive limit value I _G -ΔI or an active pointer is output by the control device 1 .

For the cross current i _QV , it is the redundant pointers 101/010 or 010/101 that are switched on instead of the normal zero pointers with the switch positions 000/000 or 111/111 in order to drive the cross current in the negative or positive direction for the purpose of symmetrization .

For the cross current i _QW , it is the redundant zero pointers with the switch positions 110/001 or 001/110 that are switched on during the period of one of the normal zero pointers in order to drive the cross current i _QW in the negative or positive direction for the purpose of symmetrization.

If the positive or negative limit values ± I _{G are} reached or exceeded for a predetermined period of time without a zero pointer setting command being reported by the control device 1 , an exception is also switched to the appropriate or the corresponding zero pointer when there is an active pointer.

FIG. 3 shows the hysteresis of the zero-current or cross-current limit value comparators, by means of which the current to be reduced is only reduced up to a limit value reduced by a current measure ΔI.

In FIG. 4, the time course, for example, the cross current i _QU shown over the time t, where here too the switching hysteresis with the lowering of the current i _QU from the positive limit value I _G to a reduced limit -I _G + .DELTA.I is shown.

In the circuit arrangements shown in FIG. 1 or FIG. 2, although IGBT elements are shown as semiconductor power switches, the method according to the invention is of course also applicable to other power semiconductor switches that can be switched off, such as bipolar transistors, MOSFET, GTO thyristors,. . . etc. applicable. The specified method also applies not only to inverters that have a common intermediate circuit, but also to inverters that are fed via separate intermediate circuits. (This is then a special case in which the control of the zero current by the cross-flow control device 9 is omitted.)

The steepness of the cross-current change during the redundant zero vector set for cross-current and zero-current control (depending on the inductance value L _q ) can be very large, so that a timely interruption when the limit value ± (I _G -ΔI) is reached leads to high dynamic demands on the comparators 50 PO, 50 NU. . . 50 PW, 50 NW and the additional control 2 leads. In this case, it is better to forego the comparator hysteresis and instead to estimate the time Δt necessary to reduce the cross-current and the zero-current from ∓I _G to ± (I _G -ΔI) off-line. The additional control 2 then has the task of setting the redundant zero pointer for the predetermined time period Δt.

Claims (6)

1.Universal method for symmetrizing the cross-current distribution in two self-commutated inverters constructed in the same way from power semiconductor switches, the output terminals of which are connected to the strings of a three-phase load via inductors and whose power semiconductor switches for each strand fed are driven in the same direction in parallel by a control device with potential setting commands , characterized in that the switching states corresponding to active pointers in the room pointer representation at the output terminals of the first / second inverter (WRA, WRB) in the same terminal sequence (UVW) 100/100; 110/110; 010/010; 011/011; 001/001 and 101/101 (with 1 = output terminal connected to the DC positive pole and 0 = output terminal connected to the DC negative pole) are always implemented as a priority by the control device, while instead of the usual zero pointer (zero voltage at the output terminals) with the switching states 000 / 000 or 111/111 in the case of a cross current exceeding a positive or negative cross current limit value (i _QU ... I _QW ) in an inverter string as long as a zero pointer of the six switch positions 100/011; 010/101; 001/110; 110/001; 101/010; 011/100 is selected until the excessive cross current (i _QU ... I _QW ) has set itself to a reduced cross current limit lying within the cross current limits and in the case of a zero current exceeding a positive or negative zero current limit (i _q0 ) a zero pointer with one of the two switch positions 000/111 or 111/000 is selected until the excessive zero current (i _q0 ) has set itself to a reduced zero current limit value within the zero current limit values. 2. The method according to claim 1, characterized in that when the zero current and / or cross current limit values for a predetermined period of time are exceeded by the zero or a cross current without a command to issue a zero pointer from the control device ( 1 ) , a zero pointer to reduce the zero or cross current is also specified instead of an active pointer. 3. The method according to any one of claims 1 or 2, characterized, that the reduced zero current limit values and / or cross current Limit values should always be selected so that the zero current and / or the cross current is reached when this reduced limit value is reached Direction has changed. 4. Circuit arrangement for performing the method according to claim 1, characterized in

• - Current converters ( 8 UA to 8 WA, 8 UB to 8 WB) are provided at the phase outputs of the inverters (WRA, WRB), each of which is connected on the secondary side to a comparator ( 6 ) within a cross-current control device ( 9 ),
• - That the three comparison _elements ( 6 ) is followed by a summing element ( 7 ), the output signal for forming the cross _current (i _q0 ) is divided into three by a dividing _element ( 8 ),
• - That the outputs of the three comparison elements ( 6 ) are additionally connected to three further comparison elements ( 10 ), which are also connected to the output of the dividing element ( 8 ),
• - That the output of each further of the comparison elements ( 10 ) is connected to two limit value comparators ( 50 PU, 50 NU), one of which is the output signal of one of the further comparison elements ( 10 ) with a positive cross-current limit value and the other is the output signal of one compares the further comparison elements ( 10 ) with a negative cross-current limit value,
• - That each of the limit value comparators ( 50 PU, 50 NU) is connected to one of the control devices ( 1 ) of the inverters (WRA, WRB) downstream additional control device ( 2 ), which is delivered by one of the limit value comparators ( 50 PU, 50 NU) Limit signal instead of a zero pointer of the switching position 111/111 or 000/000 output by the control device ( 1 ) a zero pointer of the switching positions 100/011; 010/101; 001/110; 110/001; 101/010; 011/100 in the sense of reducing the cross-flow,
• - That the output of the divider ( 8 ) is also connected to two further limit comparators ( 50 PO, 50 NO), one of which is the output signal of the divider ( 8 ) with a positive zero current limit and the other the output signal of the divider ( 8 ) with a negative zero current limit value,
• - And that each of the further limit value comparators ( 50 PO, 50 NO) is connected to the additional control device which, in the case of a limit value signal output by the further limit value comparators ( 50 PO, 50 NO) instead of a zero pointer of the switch positions output by the control device ( 1 ) 111/111 or 000/000 a zero pointer of the switching position 000/111 or 111/000 in the sense of a reduction in the zero current (i _q0 ).

5. Circuit arrangement according to claim 4, characterized in that the limit value comparators ( 50 NU, 50 PU, 50 NO, 50 PO) are equipped with a switching hysteresis by the positive or negative limit value and one each by a current component (ΔI) reduced limit value is formed. 6. Circuit arrangement according to claim 4, characterized in that in the case of rapid changes in cross current, the additional control device ( 2 ) is one of the zero pointers of the six switch positions 100/011; 010/101; 001/110; 110/001; 101/010 or 011/100 for an off-line estimated time period.