DE4108406A1 - Thyristor control circuit for alternating current supplies - utilises up-down counter and ROM look-up table to define repetitive switching sequence used to trigger thyristor - Google Patents

Abstract

A synchronisation signal is obtd. from a resistor (Rsyn) and passed to a half-wave detector (9) and a crossing point detector (11). The former detects the half-wave periodicity and passes a timing signal (Th) to a timing signal generator (10) that generates a synchronising pulse (Tsyn) which is passed via two AND gates (G1,G2) to an up/down counter (5) and to a shift register and buffer (7). The output of the up/down counter is passed via an address bus (5a) to a ROM (4) contg. a conduction sequence look-up table. Each word in the look-up table comprises a conduct/not conduct sequence, the average value of which is proportional to the up/down counter address value. The addressed word is passed to the shift register and clocked by crossing point detector impulses onto the trigger contact of an external thyristor (2) (via an amplifier (8)), thus turning the thyristor on and off in proportion to the value stored on the up/down counter. If desired supply voltage (c) is greater than the actual supply voltage (d) an amplifier (K) enables the first gate (G1), allowing the synchronising pulses to increase the value stored on the up/down counter, thereby reducing the average thyristor conduction time, whereas if the desired supply voltage (c) is less than the actual supply voltage (d), the amplifier enables the second gate (G2) via an inverter (G4), thereby reducing the value stored on the up/down counter, reducing the average thyristor conduction time. USE/ADVANTAGE - For electric heating. Inclusion of up/down counter permits finely graduated adjustments to be made to output power setting, reducing adjustment response time and improving accuracy.

Description

The invention relates to a method for controlling the from an AC power source to an ohmic load in Lei delivered several adjustable power levels stung according to the preamble of claim 1.

A power control can be achieved through a phase control control, which is a quasi-continuous regulation leaves. At high powers, however, such a re success because of the harmonics generated and there caused by interference, so that elaborate filter circuits would be required, whereby however, the economic benefits are questioned would. It is therefore using a zero voltage scarf ters the alternating current feeding the load in its Zero crossings of the AC voltage on and off switches so that there is no phase control.

A regulation, for example the heating power of a high performance electric heater by on and off switch, but requires a relatively high switching frequency around a certain setpoint of a heating element compliance. However, this affects the high Performance of such a heater the mains voltage due to their impedance by causing unwanted flickering electric light bulbs. The one from the  Utilities approved switching frequency therefore the lower the higher the lei to be switched stung is. For example, the so-called Flicker standard according to VDE for the control of a heating element 800 W cycle time in seconds, with a heating output of 2 kW, however, one cycle time of about 20 seconds.

However, this requirement can apply to thermally fast La most, such as a hot air gun, for Burn out their heating coil, here would be one Cycle time of around 600 ms required.

It was therefore on the part of the utilities let the power change every 3 grid periods to vary one third of the total output. This is to be explained with the following Table 1:

Table 1

In this table, the digits 1 to 6 denote six half-periods, that is, three network periods. This first line of this table shows three groups, each with three network periods. In line 1, power is taken up by the load during the three periods of each group, that is to say during all half-periods 1 to 6 of each group, so this corresponds to the maximum power of 100%. In the illustration, the abbreviation "P" or "N" stands for the positive or negative half-wave of the mains voltage. Line 2 shows the case in which the load consumes a third less power, i.e. 66% of the maximum power. This is achieved by the fact that no power is supplied to the load in the three-period groups, that is to say every three network periods during the third and sixth half-periods. Finally, according to line 3, the power is reduced to 33% by no power being taken up by the load in any three-period group, even during the second and fifth half-period.

However, this method has the disadvantage that only a very rough control of performance is possible what inevitably excessive overshoot, for example leads to a temperature control.

Accordingly, the invention is based on the object Process for power control of the aforementioned Specify a small change in performance allows.

This task is characterized by the characteristics of claim 1 solved.

The essence of the invention is therefore a Pe perform group control in such a way that for each performance level a certain sequence of Control pulses are provided for the controllable switch is, this control pulse train after a be agreed number of Netzpe grouped cycles repeated. The fixed for each performance level put control pulse train is in a memory, preferred  a ROM memory or one of these ROM memories corresponding combinatorial logic filed. A before up-down counter with a number of counting steps which corresponds to the number of power levels, now serves the appropriate from the ROM memory Select control pulse train. This is fiction by assigning each counter level to one Control pulse sequence accomplished so that increase with the value of the counter also the value of the control power associated with the pulse train increases. In Ab dependency of an actual setpoint comparison, for example as a temperature control by comparing the measured temperature with a setpoint of the tempera tur, the up-down counter counts up or backwards, depending on whether the actual value of the power over or below the nominal value of the power. Is with for example the actual value of the power is too large due to the countdown of the up-down count lers a control pulse sequence from the memory to the on Control circuit for the controllable switch turned on read that is associated with a lower power. This is carried out until the actual value Corresponds to the setpoint.

This inventive method allows a belie bige reduction in the difference in value between two neighboring performance levels, depending on how many groups of Network periods are provided or how many periods includes a group.

An advantageous further development is preferred of the method according to the invention, each counting step associated with the up-down counter Control pulse train from the memory in a shift regi  most read. For this, a clock signal is generated whose frequency corresponds to the group period. Preferential becomes the phase position of the for the shift register required shift cycle selected so that the Infor mation in the shift register shortly before a zero crossing the AC voltage is pushed on.

Furthermore, according to a particularly advantageous embodiment of the invention a synchronization clock generated, the rising edge of the clock for the Up-down counter and its falling edge the clock for the transfer of the control pulse sequence represents the memory in the shift register. Consequently it is ensured that the associated control pulse train in the shift register is taken over.

Finally, according to a last one, it is particularly advantageous adhere to further development of the invention a period number m = 3 is provided, which is based on Table 1 contains basic patterns explained, but by the inventor period group control according to the invention is superimposed.

In the following, the invention is based on an embodiment approximately example in connection with the figures tert and be represented. Show it:

Fig. 1 is a block diagram of a circuit arrangement for performing the method according to the invention and

Fig. 2 pulse and timing diagrams for explaining the operation of the circuit arrangement of FIG. 1.

As stated above, this includes inventions method according to a period group control n groups of m network periods each. As an example of Explanation of the method according to the invention is intended Number of groups of n = 5, each with m = 3 network periods be accepted. With a 50 Hz AC power source there is a group period of 300 ms. With a Such a group period can be according to Table 2 Realize 16 performance levels. The form of presentation this table 2 corresponds to that of the beginning listed table 1. The listed in table 1 led basic pattern is also the ge with Table 2 ge showed patterns. After that there is a group period of 5 groups with group numbers 1 to 5, where each group comprises 3 network periods and with the Abbreviation "PNPNPN" are shown with which together with the explanation of Table 1 Importance.

According to this table 2, power level 16 corresponds to the highest power to be absorbed by the load, i.e. 100%. Thereafter, the load takes power during each half period of each group. In power stage 15 , 93% of the maximum power is absorbed by no power being taken up by the load in only the fifth group during the positive half-wave of the second period and the negative half-wave of the third period. This is carried out successively for all groups up to group number 1, reducing the power consumption up to power level 11 by 66%. From power level 10 with 59% of the maximum power, no additional power is now taken up by the load in the fifth group during the negative half-wave of the first period and the positive half-wave of the third period. This is again carried out successively for all groups up to the first group, with a step-by-step reduction in performance down to performance level 6 with 33%. With power level 5 of 27% of the maximum power, no power is now taken up during the fifth group. Successively no power is now also consumed for the other groups 4 to 1, so that in power stage 2, only the first group consumes 6% of the maximum power from the load during the positive half-wave of the first period and the negative half-wave of the second period becomes. The first power level is characterized in that the power consumption is zero. With a group period of five groups, each with six network periods, 16 power levels can be achieved with only three power levels according to the method explained in Table 1.

The circuit arrangement according to FIG. 1 serves to carry out the method according to the invention on the basis of a control pattern according to Table 2, in particular the circuit arrangement denoted by reference number 3 , which can be implemented integrally. This circuit arrangement 3 controls via a connection a the control electrode of a triac 2 , which is connected in series with a load R _L to an alternating current source 1 with a mains voltage U _mains . This circuit arrangement 3 comprises a ROM 4 , an up-down counter 5 , a control circuit 6 for the triac 2 , a half-wave detector 9 , a shift clock generator 10 , a zero point detector 11 , a comparator K and two AND gates G 1 and G 2 and a negation element G 4 . Furthermore, the control circuit 6 includes a shift register 7 , an AND gate G 3 and an output stage 8th

The control pulse sequences listed in Table 2 for a group period are now stored in the ROM memory 4 for each power level 1 to 16. An empty space in the sequence "PNPNPN", for example "PN NP", means that the triac does not carry any current during these half-periods. Such a control pulse sequence is therefore a sequence of logical ones and zeros. The up-down counter 5 has 16 counting steps according to the number of power stages. A power level can thus be assigned to each counting step, so that, for example, the counting step "10" corresponds to power level 10. The fully counted up-down counter 5 thus shows the highest power level 16.

The value of the current counter reading of the forward-backward counter 5 is supplied via a line 5 a to the ROM memory 4 for selection of the corresponding control pulse sequence. The selected control pulse sequence is then taken over a line 4 a in the shift register 7 .

C and d at the terminals of the circuit assembly 3, a target value V _set to an actual value and U _is integrally inserted. The voltage value of U _is of the actual value may be generated at play, via a peeled to the load R _L in series th shunt resistor or generated with a temperature sensor also contact temperature control. The actual and setpoint values are fed to the inputs of the comparator K. The output of this comparator K is connected to the first input of the AND gate G 1 and, via the negation element G 4, also to the first input of the AND gate G 2 . The output of the first-mentioned AND gate G 1 is fed to the forward input U _V and the output of the second-mentioned AND gate G 2 to the reverse input of the forward-backward counter 5 . The second outputs of the two called AND gates G 1 and G 2 are connected downstream of the shift clock generator 10 , the output signal of which is also supplied to the shift register 7 as a transfer clock. How this is done in detail is explained below.

The shift clock generator 10 is finally controlled by a half-wave detector 9 . This half-wave detector 9 and the zero point detector 11 are connected via a connection b of the circuit arrangement 3 and a resistor R _syn to the AC power source 1 . The zero point signal of the zero point detector 11 is supplied as a shift clock to the shift register 7 and the first input of the AND gate G 3 of the control circuit 6 . The second input of this AND gate G 3 is di rectly connected to the shift register 7 , while the output of this AND gate G 3 drives the output stage 8 for the triac 2 .

In the following, the operation of the circuit arrangement according to FIG. 1 in connection with the pulse diagrams according to FIGS . 2a to 2d will be explained. The diagram of Fig. 2a shows the curve of the alternating voltage U _mains five groups of three mains periods with a group period is 300 ms, and subsequently the rest of the network clamping voltage for two other groups. This network voltage U _network is applied via the resistor R _{syn to} both the half-wave detector 9 and the zero point detector 11 . The half-wave detector 9 only detects the positive half-waves and generates the clock sequence T _{h shown} in the diagram in FIG. 2b. In contrast, the zero detector 11 derives from this mains voltage U _mains 2d drawn zero pulses in Fig. T _Φ from which each mark the zero crossing of the AC voltage. The shift clock generator 10 derives from the clock signal T _{h of} the half-wave detector 9 a synchronization clock signal T _syn with a clock sequence according to FIG. 2c. The clock pulse of this clock signal T _syn appears only at the beginning of the first group of a group period, that is, after 300 ms. As already explained above, this clock signal is fed to the two inputs of the AND gates G 1 and G 2 . If the actual value is below the target value, an H level appears at the output of the comparator K, with the result that the forward input U _V is controlled by the AND gate G 1 with the next pulse of the synchronization clock T _syn . However, this control takes place with the rising edge of this clock pulse. At the same time, however, this clock pulse is also supplied to the shift register 7 for the purpose of transferring the control pulse sequence corresponding to the counting step into the shift register 7 . However, this takes place with the falling edge of this clock pulse of the synchronization clock T _syn . So if this up-down counter 5 switches example from the fifth counting step to the sixth counting step, the control pulse sequence for the power stage 6 in the shift register 7 is only taken with the falling edge of the clock pulse triggering this counting step of the synchronization clock T _syn . The H level present in this case at the output of the comparator K is applied as an L level to the first input of the AND gate G 2 by the negation element G 4 , so that this drives the backward input U _{R of} the forward - Down counter 5 un remains. The now stored in the shift register 7 information of the control pulse sequence for the power stage 6 is read in time with the clock signal T _{Φ of} the zero point detector 11 and supplied to one input of the AND gate G 3 . Since this clock signal T _{Φ is also} supplied to the other input of this AND gate G 3 , the control pulses of the control pulse sequence are each forwarded with the zero point signal of the output stage 8 for controlling the triac 2 . An H level is present at the output of the comparator K as long as the actual value is below the setpoint; at the same time counts the up-down counter 5 forward, so that this always turns on the next higher power level.

If the actual value now reaches the setpoint and even exceeds it, the output of the comparator K switches to L level, so that an H level is now present at one input of the AND gate G 2 . With the next rising edge of a clock pulse of the synchronization pulse T _syn, the up-down counter 5 counts backwards, which means that a control pulse sequence of a lower power level with the falling edge of the same clock pulse is transferred to the shift register 7 in accordance with the value of the counting step. With the help of the clock signal T _{Φ of} the zero point detector 11 , the new information from the shift register 7 is supplied to the output stage 8 .

With this power control according to the invention, exact compliance with a desired setpoint can be ensured. According to the embodiment shown in Table 2, a total load of approximately 1800 W can be switched. To improve the control properties, the comparator provided in FIG. 1 can have hysteresis properties.

Furthermore, the assignment of the counting steps to the performance stages made in the exemplary embodiment according to FIG. 1 can be reversed, so that a decreasing value of the corresponding power level is assigned with increasing value of the counting level. The associated logic must be adapted in a manner known to those skilled in the art.

Finally, the method according to the invention is also optimally suitable for heating solder baths.

Claims (5)

1. Method for controlling the power from an alternating current source ( 1 ) to an ohmic load (R _L ) in several adjustable power levels by means of a controllable switch ( 2 ) connected in series to the load (R _L ), which is only in zero crossing the AC voltage of the AC power source ( 1 ) is switched, characterized in that using a memory ( 4 ), an up-down counter ( 5 ) with a number corresponding to the number of adjustable power levels, and a control circuit ( 6 ) for following the controllable switch ( 2 ):

• a) for each power level one with the number of n (n 0) groups of m (m 1) periods of the AC voltage of the AC source ( 1 ) repeating control pulse sequence for the controllable switch ( 2 ) in the memory ( 4 ) sets,
• b) each counting step of the up-down counter ( 5 ) is assigned a control pulse sequence stored in the memory ( 4 ) in such a way that the value of the power stage also increases as the value of the counting step increases,
• c) a first and a second clock signal are also generated, the clock frequencies of which each correspond to the duration of the group period of n groups, the second clock signal tracking the first clock signal by an angle of less than π / 2,
• d) furthermore one of the physical quantity to be controlled via the power absorbed by the load (R _L ), e.g. B. temperature, corresponding actual value generated, which is compared with a target value,
• e) if the actual value is above or below the setpoint, the up-down counter ( 5 ) counts in the cycle of the first clock signal backwards or forwards until the actual value speaks to the setpoint, the control pulse sequences corresponding to the incremented counting steps the second clock signal is taken from the memory ( 4 ) into the control circuit ( 6 ),
• f) the control circuit ( 6 ) leads in each case in the zero crossing the individual control pulses of the control pulse sequence to be fed to the controllable switch ter ( 2 ).

2. The method according to claim 1, characterized in that

• g) that the control circuit ( 6 ) has a shift register ( 7 ) into which the control pulse sequence is adopted with the second clock signal,
• h) that a shift clock for the shift register ( 7 ) is generated with a frequency corresponding to the half period of the AC voltage,
• i) that a zero point signal is generated from the AC voltage and
• j) that the output signal of the shift register ( 7 ) is rounded off with the zero point signal and then fed to the controllable switch ( 2 ).

3. The method according to claim 2, characterized in
that the phase position of the shift clock is selected so
that the information in the shift register ( 7 ) is shifted before each zero crossing of the AC voltage. 4. The method according to any one of the preceding claims, characterized in that a synchronization clock (T _syn ) is generated, the pulses with the rising or falling edge represent the first or second clock signal and that this synchronization clock (T _syn ) by means of a Half-wave detector ( 9 ) and a shift clock generator ( 10 ) is generated. 5. The method according to any one of the preceding claims, characterized in

• a) that for a number of periods m = 3 for gradual power reduction successively in each group during the positive half-wave of the second period and the negative half-wave of the third period, the load (R _L ) does not absorb any power and
• b) that the load (R _L ) does not consume any power during the negative half-wave of the first period and the positive half-wave of the third period in order to further gradually reduce the power in each group, and
• c) that finally, for further gradual power reduction in succession, the load (R _L ) does not consume any power during the positive half-wave of the first period and the negative half-wave of the second period.