DE4025622A1 - Terminal contact for integrated circuit semiconductor systems - comprises barrier-, undoped gold and gold rich eutectic gold-tin doped-layers on conducting path - Google Patents

Terminal contact for integrated circuit semiconductor systems - comprises barrier-, undoped gold and gold rich eutectic gold-tin doped-layers on conducting path

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Publication number
DE4025622A1
DE4025622A1 DE4025622A DE4025622A DE4025622A1 DE 4025622 A1 DE4025622 A1 DE 4025622A1 DE 4025622 A DE4025622 A DE 4025622A DE 4025622 A DE4025622 A DE 4025622A DE 4025622 A1 DE4025622 A1 DE 4025622A1
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Prior art keywords
gold
layer
tin
semiconductor systems
undoped
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DE4025622A
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German (de)
Inventor
Hans-Hinnerk Dipl Phy Steckhan
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Siemens AG
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Siemens AG
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Priority to DE4025622A priority Critical patent/DE4025622A1/en
Publication of DE4025622A1 publication Critical patent/DE4025622A1/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05666—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01068—Erbium [Er]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

Contact (I) with barrier layer (4) and contg. gold and tin, has an undoped gold layer (7-1) in the region neighbouring (4) and a gold-rich eutectic gold-tin-doped layer (7-3) contg. 80 wt. % gold and 20 wt. % tin in a region not adjacent to (4). Prepn.of (I) comprises applying gold layer to (4) and applying tin layer (7) and doping at 330-420 deg. C for up to 10 min. pref. in a non-oxidising atmos. Pref. intermediate layer (7-2) in the form of a gold-tin phase is between (7-1) and (7-3).

Description

Die vorliegende Erfindung betrifft einen Anschlußkontakthöcker für Halbleitersysteme nach dem Oberbegriff des Patentanspruchs 1 sowie ein Verfahren zu dessen Herstellung nach dem Patentan­ spruch 3.The present invention relates to a terminal bump for semiconductor systems according to the preamble of patent claim 1 and a method for its production according to the patent saying 3.

Bekannte Verbindungen zwischen Anschlußbändchen und Anschluß­ kontakthöckern von Halbleitersystemen bei Mikropack-Bauformen erfolgen durch Thermokompression von Gold zu Gold, d. h., von mit Gold beschichteten Anschlußbändchen und Gold-Anschlußkon­ takthöckern auf dem Halbleitersystem oder durch Löten in einem Gold/Zinn-Eutektikum, d. h., durch Anlöten von mit Zinn beschich­ teten Anschlußbändchen an Gold-Anschlußkontakthöckern des Halb­ leitersystems. Beide Verfahren besitzen wesentliche Nachteile. Bei der Thermokompression ist zur Herstellung der Verbindung ein hoher Druck erforderlich, der zu Kraterbildungen im Sili­ zium des Halbleitersubstrats oder zu Defekten in der Substrat- Passivierung führen kann. Beim Löten mittels eines konventio­ nellen Gold/Zinn-Eutektikums muß die Beschichtung mit Zinn der gewöhnlich aus Kupfer bestehenden Anschlußbändchen in einer sehr geringen Dicke von unterhalb 1 µm erfolgen, wodurch die Lagerzeit der Mikropack-Bauformen vor ihrer Weiterverarbeitung durch Einbau beispielsweise SMD-Systeme reduziert wird.Known connections between connection ribbon and connection contact bumps of semiconductor systems in micropack designs are done by thermal compression from gold to gold, d. i.e. from with gold-coated connection ribbon and gold connection con clock bumps on the semiconductor system or by soldering in one Gold / tin eutectic, d. i.e. by soldering tin tied connection tapes on gold connection bumps of the half conductor system. Both methods have major disadvantages. Thermocompression is used to make the connection a high pressure is required, which leads to crater formation in the silo zium of the semiconductor substrate or defects in the substrate Passivation. When soldering using a convention The gold / tin eutectic must be coated with tin usually made of copper connection strips in one very small thickness of less than 1 micron, which makes the Storage time of the micropack designs before further processing is reduced by installing, for example, SMD systems.

Der vorliegenden Erfindung liegt die Aufgabe zugrunde, einen Anschlußkontakthöcker sowie ein Verfahren zu seiner Herstellung anzugeben, bei dem die genannten Verbindungen durch geringen Verbindungsdruck und flußmittelfrei herstellbar sind, konven­ tionelle mit Gold beschichtete Anschlußbändchen verwendbar sind und auf den Anschlußbändchen eine möglichst geringe Gold­ dicke gewährleistet ist. The present invention is based on the object Terminal bumps and a method for its production to indicate, in which the connections mentioned by small Connection pressure and flux-free can be produced, conv tional gold-coated connecting tapes can be used are and as little gold as possible on the connecting tapes thickness is guaranteed.  

Diese Aufgabe wird bei einem Anschlußkontakthöcker der eingangs genannten Art erfindungsgemäß durch die Merkmale des kennzeich­ nenden Teils des Patentanspruchs 1 gelöst.This task is at the beginning of a contact bump mentioned type according to the invention by the features of the character nenden part of claim 1 solved.

Eine Weiterbildung des erfindungsgemäßen Anschlußkontakthöckers ist Gegenstand eines Unteranspruchs.A further development of the terminal bump according to the invention is the subject of a subclaim.

Ein Verfahren zur Herstellung eines erfindungsgemäßen Anschluß­ kontakthöckers ist durch die Merkmale des Patentanspruchs 3 ge­ kennzeichnet.A method for producing a connection according to the invention contact hump is ge by the features of claim 3 indicates.

Die Erfindung wird im folgenden anhand eines in den Fig. der Zeichnung dargestellten Ausführungsbeispiels näher erläutert. The invention will in the following with reference to an in FIGS. The drawing, the illustrated embodiment explained in more detail.

Es zeigt:It shows:

Fig. 1 eine schematische Darstellung eines erfindungsgemäßen Anschlußkontakthöckers auf einem Halbleitersystem vor dessen endgültiger Fertigstellung; und Figure 1 is a schematic representation of a terminal bump according to the invention on a semiconductor system before its final completion. and

Fig. 2 einen solchen Kontakthöcker nach seiner Fertigstellung. Fig. 2 such a bump after its completion.

Gemäß Fig. 1 ist auf einem schematisch dargestellten Halbleiter­ substrat 1 in konventioneller Weise eine üblicherweise aus Alu­ minium hergestellte Leiterbahn 2 vorgesehen, die durch eine Isolationsschicht 3 begrenzt ist. Über die Leiterbahn 2 und die Isolationsschicht 3 verläuft eine Barriereschicht, welche beispielsweise durch Titan/Wolfram gebildet ist. Auf dieser Barriereschicht 4 ist eine weitere Isolationsschicht 5 vorge­ sehen, welche oberhalb der Leiterbahn 2 eine Öffnung für den herzustellenden Anschlußkontakthöcker aufweist.According to Fig. 1 to a schematically shown semiconductor substrate 1 in a conventional manner typically provided from alu minium prepared conductor 2, which is bounded by an insulation layer 3. A barrier layer, which is formed for example by titanium / tungsten, runs over the conductor track 2 and the insulation layer 3 . On this barrier layer 4 , another insulation layer 5 is easily seen, which has an opening above the conductor track 2 for the terminal bump to be produced.

Erfindungsgemäß wird dieser Anschlußkontakthöcker in folgender Weise hergestellt: Es wird auf die Barriereschicht zunächst ei­ ne Goldschicht 6 aufgebracht, welche mit einer Zinnschicht 7 überzogen wird.According to the invention, this terminal bump is produced in the following manner: It is first applied to the barrier layer ei ne gold layer 6 , which is coated with a tin layer 7 .

Diese Gold/Zinn-Doppelschicht wird nun erfindungsgemäß in einer nicht oxidierenden Atmosphäre einem Legierungsprozeß unterzo­ gen, wobei die Legierungsbedingungen folgendermaßen gewählt sind: Es ist zu vermeiden, daß sich ein zinnreiches Gold/Zinn- Eutektikum ergibt, da dessen Schmelzpunkt von 217°C nachteilig ist. Es müssen sprüde Gold/Zinn-Zwischenphasen vermieden werden an der mit den Anschlußbändchen zu verbindenden Seite des An­ schlußkontakthöckers, d. h., an der vom Halbleitersubstrat 1 ab­ gewandten Seite soll sich ein goldreiches Gold/Zinn-Eutektikum mit einem Goldanteil von 80 Gew.% Gold und 20 Gew.% Zinn bilden, in dem der Barriereschicht 4 benachbarten Bereich des Anschluß­ kontakthöckers soll eine ausreichende unlegierte Goldschicht verbleiben, die auch nach einer Lagerung bei hohen Temperaturen erhalten bleibt.This gold / tin double layer is now subjected to an alloying process according to the invention in a non-oxidizing atmosphere, the alloying conditions being chosen as follows: It is to be avoided that a tin-rich gold / tin eutectic results, since its melting point of 217 ° C. is disadvantageous is. Brittle gold / tin intermediate phases must be avoided on the side of the contact bump to be connected to the connecting tapes, ie, on the side facing away from the semiconductor substrate 1 , there should be a gold-rich gold / tin eutectic with a gold content of 80% by weight gold and form 20% by weight of tin, in the region of the connection bump adjacent to the barrier layer 4 , a sufficient unalloyed gold layer should remain, which is retained even after storage at high temperatures.

Diese erfindungsgemäßen Eigenschaften des Anschlußkontakthöckers werden dadurch realisiert, daß die Legierung durch eine Tempera­ turbehandlung in einem Temperaturbereich von 330 bis 420°C für eine Zeit von bis zu zehn Minuten durchgeführt wird. Der Legie­ rungsvorgang erfolgt in einer nichtoxidierenden Atmosphäre, wo­ bei die vorgenannten Temperatur- und Zeitbedingungen zur Reali­ sierung der obengenannten Eigenschaften des Anschlußkontakt­ höckers wesentlich sind, damit eine schnelle Diffusion von Gold in flüssiges Zinn erfolgt.These properties of the terminal bump according to the invention are realized in that the alloy by a tempera Turbo treatment in a temperature range from 330 to 420 ° C for a time of up to ten minutes is carried out. The Legie The process takes place in a non-oxidizing atmosphere where at the aforementioned temperature and time conditions for reali sation of the above properties of the connector Höckers are essential for a quick diffusion of gold done in liquid tin.

Ein fertiger erfindungsgemäßer Anschlußkontakthöcker ist in Fig. 2 dargestellt, in der gleiche Elemente wie in Fig. 1 mit gleichen Bezugszeichen versehen sind. In dem der Barriere­ schicht 4 abgewandten Bereich des Anschlußkontakthöckers, d. h., in dem Bereich, in dem eine Verbindung mit nicht dargestellten Anschlußbändchen durchgeführt werden soll, befindet sich eine goldreiche eutektische Gold/Zinn-Legierungsschicht 7-3 mit einem Goldanteil von 80 Gew.% und einem Zinnanteil von 20 Gew.%. In dem der Barriereschicht 4 benachbarten Bereich befindet sich ei­ ne unlegierte Goldschicht 7-1.A finished connection bump according to the invention is shown in Fig. 2, in which the same elements as in Fig. 1 are provided with the same reference numerals. In the area of the terminal bump facing away from the barrier 4 , that is to say in the area in which a connection is to be made with terminal strips (not shown), there is a gold-rich eutectic gold / tin alloy layer 7 -3 with a gold content of 80% by weight. and a tin content of 20% by weight. In which the barrier layer 4 adjacent area is egg ne unalloyed gold Layer 7 -. 1

Bei den obengenannten Bedingungen ergibt sich vorzugsweise zwi­ schen den vorgenannten Schichten 7-1 und 7-3 eine Schicht 7-2 in Form einer Gold/Zinn-Phase, welche durch einen Anteil von 89,4 Gew.% Gold und 10,6 Gew.% Zinn gekennzeichnet ist.In the above conditions, there is preferably Zvi rule the aforementioned layers 7 - 1 and 7 - 3 a layer 7 - 2 in the form of a gold / tin phase, which by a proportion of 89.4% by weight of gold and 10.6 wt. % Tin is marked.

Claims (4)

1. Anschlußkontakthöcker für Halbleitersysteme, insbesondere Halbleitersysteme von integrierten Schaltkreisen, der auf eine mit einer Barriereschicht (4) versehene Leiterbahn (2) aufge­ bracht und aus Gold und Zinn zusammengesetzt ist, da­ durch gekennzeichnet, daß er eine unlegier­ te Goldschicht (7-1) in dem zur Barriereschicht (4) benachbar­ ten Bereich und eine goldreiche eutektische Gold/Zinn-Legie­ rungsschicht (7-3) mit 80 Gew.% Gold und 20 Gew.% Zinn in dem der Barriereschicht (4) abgewandten Bereich aufweist.1. Connection bump for semiconductor systems, in particular semiconductor systems of integrated circuits, of up to a provided with a barrier layer (4) strip conductor (2) is composed introduced and of gold and tin as characterized by that it has an unalloyed th gold layer (7 - 1 ) in the area adjacent to the barrier layer ( 4 ) and a gold-rich eutectic gold / tin alloy layer ( 7 - 3 ) with 80% by weight of gold and 20% by weight of tin in the area facing away from the barrier layer ( 4 ). 2. Anschlußkontakthöcker nach Anspruch 1, dadurch ge­ kennzeichnet, daß sich zwischen der unlegierten Goldschicht (7-1) und der eutektischen Legierungsschicht (7-3) eine Zwischenschicht (7-2) in Form einer Gold/Zinn-Phase be­ findet.2. Connection bumps according to claim 1, characterized in that between the non-alloyed gold layer (7 - 1) - an intermediate layer (7 - 2) in the form of a gold / tin phase will be and the eutectic alloy layer (3 7). 3. Verfahren zur Herstellung eines Anschlußkontakthöckers nach Anspruch 1 und/oder 2, dadurch gekennzeich­ net, daß auf die auf der Leiterbahn (2) befindliche Barriere­ schicht (4) eine Goldschicht (6) und auf die Goldschicht (6) eine Zinnschicht (7) aufgebracht wird und daß sodann eine Le­ gierungstemperaturbehandlung in einem Temperaturbereich von 330 bis 420°C für eine Zeit von bis zu zehn Minuten durchge­ führt wird.3. A method for producing a terminal bump according to claim 1 and / or 2, characterized in that on the conductor track ( 2 ) located layer ( 4 ) a gold layer ( 6 ) and on the gold layer ( 6 ) a tin layer ( 7th ) is applied and that then a Le alloy temperature treatment in a temperature range of 330 to 420 ° C for a period of up to ten minutes is carried out. 4. Verfahren nach Anspruch 3, dadurch gekenn­ zeichnet, daß die Legierungstemperaturbehandlung in einer nichtoxidierenden Atmosphäre durchgeführt wird.4. The method according to claim 3, characterized records that the alloy temperature treatment in a non-oxidizing atmosphere.
DE4025622A 1990-08-13 1990-08-13 Terminal contact for integrated circuit semiconductor systems - comprises barrier-, undoped gold and gold rich eutectic gold-tin doped-layers on conducting path Withdrawn DE4025622A1 (en)

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DE4025622A DE4025622A1 (en) 1990-08-13 1990-08-13 Terminal contact for integrated circuit semiconductor systems - comprises barrier-, undoped gold and gold rich eutectic gold-tin doped-layers on conducting path

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DE4025622A DE4025622A1 (en) 1990-08-13 1990-08-13 Terminal contact for integrated circuit semiconductor systems - comprises barrier-, undoped gold and gold rich eutectic gold-tin doped-layers on conducting path

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4224012C1 (en) * 1992-07-21 1993-12-02 Heraeus Gmbh W C Solderable electric contact element - has silver@-tin@ alloy layer below gold@-tin@ solder alloy layer
WO1996016442A1 (en) * 1994-11-17 1996-05-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Core metal soldering knob for flip-chip technology
EP0717441A3 (en) * 1994-12-13 1997-05-02 At & T Corp Method of solder bonding a body, e.g. a silicon chip, to another body
EP0994508A1 (en) 1998-10-12 2000-04-19 Shinko Electric Industries Co. Ltd. Semiconductor device comprising bump contacts
WO2005086220A1 (en) * 2004-03-09 2005-09-15 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced ausn die-attach technology

Citations (5)

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DE4224012C1 (en) * 1992-07-21 1993-12-02 Heraeus Gmbh W C Solderable electric contact element - has silver@-tin@ alloy layer below gold@-tin@ solder alloy layer
WO1996016442A1 (en) * 1994-11-17 1996-05-30 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Core metal soldering knob for flip-chip technology
EP0717441A3 (en) * 1994-12-13 1997-05-02 At & T Corp Method of solder bonding a body, e.g. a silicon chip, to another body
EP0994508A1 (en) 1998-10-12 2000-04-19 Shinko Electric Industries Co. Ltd. Semiconductor device comprising bump contacts
US6344695B1 (en) 1998-10-12 2002-02-05 Shinko Electric Industries Co., Ltd. Semiconductor device to be mounted on main circuit board and process for manufacturing same device
WO2005086220A1 (en) * 2004-03-09 2005-09-15 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced ausn die-attach technology
US7608485B2 (en) 2004-03-09 2009-10-27 Infineon Technologies Ag Highly reliable, cost effective and thermally enhanced AuSn die-attach technology

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