DE4020633A1 - Circuit for time variant spectral analysis of electrical signals - uses parallel integration circuits feeding summation circuits after amplification and inversions stages - Google Patents

Abstract

The circuit processes electrical signals consisting of n sinusoidal components with variable frequency fluctuating about a known mean foi. A computation circuit is provided for each frequency component. The computation circuits integrate, the cross product of the signal and the cosine of 2xPI t/Ti w.r.t. time t, where Ti = (1 + 0.15)/foi, and feed a summation element with input multiplication factors which are selected so that compoennts yi(t) applied to the input produce minimal output signals xk(t) (i NOT = k).

Description

The invention relates to a circuit arrangement for the time-variant spectral analysis of electrical signals s (t) which are composed of sinusoidal partial oscillations (y _i (t) whose frequencies f _i fluctuate around known mean values f _i s (t) parallel n (n - known number of partial oscillations) computing circuits R _i (i = 1,..., n) is fed, which, based on a same time t, continuously one of the integral

form proportional magnitudes, which are connected to the inputs of summing elements S _k with a weighting a _ik (i, k = 1,..., n), the a _ik being adjusted in such a way that a partial oscillation y _i ( t) produces minimal output signals x _k (t) at the output of S _k (i ≠ k) ( FIG. 1). The signals x _k (t) present at the output of such a device correspond to the sub-signals y _i (t) with a _value largely independent of f _i in the range 0.85 <= f _i / f _0i <= 1.15 For all subfunctions, the same delay of the x _i (t) with respect to s (t), whereby a phase-true decomposition of the original signal is obtained in its constituent components y _i (t).

Scope of the invention

The invention relates to a circuit arrangement for spectral analysis electrical signals composed of sinuidal Partial vibrations whose frequencies around known mean values to waver, such as B. the electroencephalogram, the heart rate and other natural, especially biogenic oscillations.

Characteristic of the known state of the art

Frequency analyzers on analog and / or digital basis include for a long time the state of the art. Related to the specifics The present solution can be divided into two groups are: a) formal-mathematical analyzers that decomposition of the signal to be examined without a direct reference to the effectual constituents, and b) constituent-related Analyzers that decompose the signal in terms of content Determine deterministic components, mostly on the basis of filter banks.

For group a) the so-called Fourier analyzers can be used as a prototype be named. Their advantage is the strictly formalized one mathematical apparatus, which also serves as the basis for appropriate digital circuitry is used. Their disadvantage is essentially in that the values determined as the result not based on the actual components, but on that of an artificial orthogonal functional system. It works the process reference largely lost. Another disadvantage is that the results look at time intervals and not at times which limits the temporal resolution. When a considerable deficiency remains the presupposed stationarity see the signal, causing the investigation frequently interesting transient processes a priori outside the Contemplation remains. Cause occurring instationarities  also errors in the results.

In contrast, filter banks (group b) are mostly natural Frequency bands adjusted. Their advantage lies in their process reference and in the possibility of detection and analysis also unsteady Processes. The disadvantage is that the transmission coefficient the band filter over the set frequency range is not constant. Oscillations at the edge of the transmission range are attenuated compared to central frequencies, from which Falsifications result. To secure an approx constant transmission behavior over the entire range of possible frequencies is a partial overlap adjacent Frequency ranges can not be avoided. This results in an undesirable "Mitklingen" or "crosstalk". Due to the Demand, the partial oscillations over the area concerned Transfer phase-free, make consuming Circuit arrangements required their economic reflection in relatively high costs. Furthermore, the affects Negative arrival and decay time for each circuit negative, which in any case causes the unsteady oscillations (eg biogenic nature) always present variations of frequency and amplitude delayed in time, therefore not true to time be imaged. This is also the beginning as an advantage postulated possibility of analysis of instationarities relativized.

Object of the invention

The aim of the invention is the temporal changes of the proportions a signal consisting of sinusoidal components whose Frequencies around known averages vary, with high phase, To capture frequency and amplitude fidelity.  

Explanation of the essence of the invention

Compared with comparable solutions of the prior art is the present characterized by the following features:

• 1. The component-specific limitation of the analysis interval effected to about 1 period length of the respective partial oscillation comparatively low on and off times and a high temporal resolution.
• 2. The determination of the integration limits according to (1a) or (2a) ensures a relatively constant (independent of the actual frequency of the partial vibration) transmission _factor in the frequency range: 0.85 <= f _i / f _0i <= 1.15 according to claim 1.0.75 <= f _i / f _0i <(= 1.25 according to claim 2).
• 3. The phase-accurate resolution and the synchronization of the parallel connection to a common time t effected by means of the subsequent coupling and weighting compensation the crosstalk of the partial oscillations, whereby a satisfactory Separation also of frequencies strongly adjacent Components is achieved.

embodiment

The exemplary embodiment ( FIG. 2) relates to the decomposition of an electroencephalogram (EEG) according to claim 1 into its natural components delta, theta, alpha and beta on the basis of the following frequency ranges:

Delta: 1.75-3.5 Hz;
Theta: 3.5-7.0 Hz;
Alpha: 7.0-14.0 Hz;
Beta: 14.0-28.0 Hz.

The measured and amplified electrical signal s (t) - the EEG - is first with a preferably integrated AD converter module (eg AD 571) digitized at intervals of approximately Δt = 2.34 ms and by means of a microprocessor circuit MP₀ on their Input gate E read from the data bus DB and in a as Shift register SR₀ acting memory type one Static RAM circuit (eg U 6264) inscribed, the is connected to the processor circuit via the memory bus SB.

The used address space of the RAM is according to the period length the lowest frequency part of the spectrum - in the EEG the delta Oscillation - and the selected sampling rate Δt 128 memory locations. The usual operation of a shift register accordingly In doing so, the last 127 of the total of 128 measured values are exactly converted one memory space each (eg in the direction of a higher address space) shifted, the foremost ("oldest") value thus overwritten (removed) and the new measured value on the released last inscribed ("youngest") storage space.  

For the determination of the partial oscillations, the formation of a calculation value r _i according to (1), (1a) takes place

from the measured values of a storage area defined in SR₀. The Locations of the components are localized as follows:

for i = 1 (delta) of space 1 to memory location 128, for i = 2 (theta) of space 33 to storage space 96, for i = 3 (alpha) of space 49 to memory location 80, for i = 4 (beta) of space 57 to storage space 72.

Each component (partial oscillation) is shown in FIG. 1 is a hybrid computing circuit - each consisting of a microprocessor MP _I comparable MP₀ (see Fig. 3) for the delta oscillation MP _D , the Thetaschwingung MP _T , etc., each one of these downstream digital-to-analog converter Circuit of known design and a summing amplifier S _i with input-side sign-correct gain (see. (4) and Fig. 4) - assigned.

After the measured value recording and shift as described above, the measured values from the above-mentioned memory areas are in each block via the output port A of the processor circuit MP₀ and the respective input port E of the processor circuit MP _I for the calculation of (3) to the ith computing circuit. starting at MP _D , MP _T, etc., which then each of the i-th calculation process is initiated.

The temporal and local synchronization as well as the acknowledgment signal game for data transfer between the processor circuits  take place according to known principles of the clocked Data exchange (eg handshake) via selected peripheral Signal lines of the processor circuit, wherein the processor circuits connecting synchronization circuit SYNC under Use of commercially available integrated logic circuits, for example the low-power Schottky 74LS series. , , and decoder circuits as 74LS139 is built.

Fig. 3 shows the basic design of a microprocessor circuit MP _I , which consists essentially of a suitable microprocessor - for example, a U886 single-chip microprocessor (corresponding to Z8682) and a conventional peripheral circuit with a ROM program memory (eg 2716), a static RAM main memory (eg U6264), one input and one output data latch (eg 74ALS583) as an input or output gate, which are each connected in a known manner via circuit-internal data and address bus lines to the processor. The control lines Sync _e and Sync _a allow the above synchronization with the processor circuit MP₀ for Meßwertaufnahme, which is constructed in the same way, but is additionally connected to the operating as a shift register SR₀ RAM circuit via the memory bus SB.

The operating speed of the four processor circuits for the determination of (3) is dimensioned such that with each new input measurement value in the shift register SR₀ exactly one calculation value r _{i is available} at the output port A of the respective processor circuit MP _I. The downstream of this gate DA converter (eg AD 7520) to implement the digital computing value r _i in a z. B. recordable by recorder analog signal is connected to each of the four summation amplifier S _{i of} FIG. 1 that the respective now present analog computation signal r _i * signed by means of a per se known amplifier arrangement and weighted in the ith summation of the following table Gain factors can:

where the indices 1. , , 4 of the factors a _ik denote the components delta to beta.

Fig. 4 shows the embodiment of such a summing amplifier with weighted inputs, wherein for the marked amplifier elements (#) commercially available integrated operational amplifier z. B. the series TL80 are used. The weighting coefficient in question is determined by the gain factor

v _ik = -R _ik2 / R _ik1 (5)

of the first inverting amplifier # 1. The following optionally interposition of another inverting Amplifier with v = -1 serves the polarity-appropriate supply of the weighted signal to the actual summing amplifier known embodiment, its sign reversal by the subsequent amplifier with v = -1 is compensated.

The electrical output signals of the overall circuit are on Output of the summation elements removed and correspond with sufficient accuracy of the time course of the components delta to beta, the latter compared to the original signal s (t) to 64 sampling points, corresponding to 150 ms, are delayed.

Claims (2)

1. Circuit arrangement for time-variant spectral analysis of electrical signals s (t), composed of n sinuidalen partial oscillations y _i (t) with variable, to a known mean f _0i fluctuating frequency f _i , characterized in that each partial vibration y _i (t) an arithmetic circuit R _i to form the integral function or a proportional thereto size, and the one summing element S _i are connected in succession, to the input of the S _i, the outputs of all R _i with the input side effective amplification factors a _ik (i, k = 1..., n) are connected and the latter are in each case adjusted so that a partial oscillation y _i (t) applied to the input of the device generates minimal signals x _k (t) (i ≠ k) at the outputs ( FIG. 1). 2. Circuit arrangement according to claim 1, characterized in that the computing circuits R _i the integral functions or form a proportional size and the output _signals x _i (t) are delayed by a dead time dependent on the center frequency f _0i .